Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation

Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation

Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing syste...

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Bibliographische Detailangaben
Hauptverfasser: HENDRIKUS JOHANNES BERNARDUS PETERS, WALTER PETER DE MUNNIK
Format: Patent
Sprache:dut ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Chip Scale Packages - CSPs - have the electronic circuits on a silicon chip (6). Electrical contact with the chip is made via bump contact points (7) under the chip and above the base carrier (4). After assembly, the package is encapsulated in insulating material. In conventional manufacturing systems, air can become trapped under the chip, leaving a void (8). In the present method a small vent hole is left in the center of the chip.