DEVICES AND METHODS FOR SIGNAL INTEGRITY PROTECTION TECHNIQUE
The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110�m pitch or less) interconnects, including the first level (e.g. the i...
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creator | YONG, Khang Choong CHEAH, Bok Eng LIM, Min Suet KONG, Jackson Chung Peng OOI, Kooi Chi |
description | The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110�m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer (312, 404, 524) with a plurality of cavities (528) to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint (310, 414, 514) is coupled to the conductive layer (312, 404, 524), and at least one interconnect joint (310, 414, 514)is isolated from the conductive layer (312, 404, 524) by a dielectric lining at least one of the cavities (528), the conductive layer (312, 404, 524) being associated to a ground reference voltage by the interconnect joint (310, 414, 514) coupled to the conductive layer (312, 404, 524). (The most illustrative drawings are Figures 3A and 3B) |
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In some embodiments, this invention provides a conductive layer (312, 404, 524) with a plurality of cavities (528) to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint (310, 414, 514) is coupled to the conductive layer (312, 404, 524), and at least one interconnect joint (310, 414, 514)is isolated from the conductive layer (312, 404, 524) by a dielectric lining at least one of the cavities (528), the conductive layer (312, 404, 524) being associated to a ground reference voltage by the interconnect joint (310, 414, 514) coupled to the conductive layer (312, 404, 524). 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In some embodiments, this invention provides a conductive layer (312, 404, 524) with a plurality of cavities (528) to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint (310, 414, 514) is coupled to the conductive layer (312, 404, 524), and at least one interconnect joint (310, 414, 514)is isolated from the conductive layer (312, 404, 524) by a dielectric lining at least one of the cavities (528), the conductive layer (312, 404, 524) being associated to a ground reference voltage by the interconnect joint (310, 414, 514) coupled to the conductive layer (312, 404, 524). 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In some embodiments, this invention provides a conductive layer (312, 404, 524) with a plurality of cavities (528) to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint (310, 414, 514) is coupled to the conductive layer (312, 404, 524), and at least one interconnect joint (310, 414, 514)is isolated from the conductive layer (312, 404, 524) by a dielectric lining at least one of the cavities (528), the conductive layer (312, 404, 524) being associated to a ground reference voltage by the interconnect joint (310, 414, 514) coupled to the conductive layer (312, 404, 524). (The most illustrative drawings are Figures 3A and 3B)</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | DEVICES AND METHODS FOR SIGNAL INTEGRITY PROTECTION TECHNIQUE |
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