PIPELINE ADC WITH SHARED GAIN STAGES

A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDB...

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Hauptverfasser: NABIHAH RAZALI, TAN KONG YEW, SHARIFAH SALEH, MOHD. SHAHIMAN SULAIMAN, ROHAYA ABDUL WAHAB, YUZMAN YUSOFF, NAZALIZA OTHMAN, ROHANA MUSA, WEE LEONG SON, HANIF CHE LAH, HASMAYADI ABDUL MAJID, ROZAIMAH BAHARIM
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creator NABIHAH RAZALI
TAN KONG YEW
SHARIFAH SALEH
MOHD. SHAHIMAN SULAIMAN
ROHAYA ABDUL WAHAB
YUZMAN YUSOFF
NAZALIZA OTHMAN
ROHANA MUSA
WEE LEONG SON
HANIF CHE LAH
HASMAYADI ABDUL MAJID
ROZAIMAH BAHARIM
description A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_MY156473A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>MY156473A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_MY156473A3</originalsourceid><addsrcrecordid>eNrjZFAJ8Axw9fH0c1VwdHFWCPcM8VAI9nAMcnVRcHf09FMIDnF0dw3mYWBNS8wpTuWF0twMcm6uIc4euqkF-fGpxQWJyal5qSXxvpGGpmYm5saOxgQVAACYQiGa</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PIPELINE ADC WITH SHARED GAIN STAGES</title><source>esp@cenet</source><creator>NABIHAH RAZALI ; TAN KONG YEW ; SHARIFAH SALEH ; MOHD. SHAHIMAN SULAIMAN ; ROHAYA ABDUL WAHAB ; YUZMAN YUSOFF ; NAZALIZA OTHMAN ; ROHANA MUSA ; WEE LEONG SON ; HANIF CHE LAH ; HASMAYADI ABDUL MAJID ; ROZAIMAH BAHARIM</creator><creatorcontrib>NABIHAH RAZALI ; TAN KONG YEW ; SHARIFAH SALEH ; MOHD. SHAHIMAN SULAIMAN ; ROHAYA ABDUL WAHAB ; YUZMAN YUSOFF ; NAZALIZA OTHMAN ; ROHANA MUSA ; WEE LEONG SON ; HANIF CHE LAH ; HASMAYADI ABDUL MAJID ; ROZAIMAH BAHARIM</creatorcontrib><description>A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; DECODING ; ELECTRICITY</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160226&amp;DB=EPODOC&amp;CC=MY&amp;NR=156473A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160226&amp;DB=EPODOC&amp;CC=MY&amp;NR=156473A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NABIHAH RAZALI</creatorcontrib><creatorcontrib>TAN KONG YEW</creatorcontrib><creatorcontrib>SHARIFAH SALEH</creatorcontrib><creatorcontrib>MOHD. SHAHIMAN SULAIMAN</creatorcontrib><creatorcontrib>ROHAYA ABDUL WAHAB</creatorcontrib><creatorcontrib>YUZMAN YUSOFF</creatorcontrib><creatorcontrib>NAZALIZA OTHMAN</creatorcontrib><creatorcontrib>ROHANA MUSA</creatorcontrib><creatorcontrib>WEE LEONG SON</creatorcontrib><creatorcontrib>HANIF CHE LAH</creatorcontrib><creatorcontrib>HASMAYADI ABDUL MAJID</creatorcontrib><creatorcontrib>ROZAIMAH BAHARIM</creatorcontrib><title>PIPELINE ADC WITH SHARED GAIN STAGES</title><description>A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAJ8Axw9fH0c1VwdHFWCPcM8VAI9nAMcnVRcHf09FMIDnF0dw3mYWBNS8wpTuWF0twMcm6uIc4euqkF-fGpxQWJyal5qSXxvpGGpmYm5saOxgQVAACYQiGa</recordid><startdate>20160226</startdate><enddate>20160226</enddate><creator>NABIHAH RAZALI</creator><creator>TAN KONG YEW</creator><creator>SHARIFAH SALEH</creator><creator>MOHD. SHAHIMAN SULAIMAN</creator><creator>ROHAYA ABDUL WAHAB</creator><creator>YUZMAN YUSOFF</creator><creator>NAZALIZA OTHMAN</creator><creator>ROHANA MUSA</creator><creator>WEE LEONG SON</creator><creator>HANIF CHE LAH</creator><creator>HASMAYADI ABDUL MAJID</creator><creator>ROZAIMAH BAHARIM</creator><scope>EVB</scope></search><sort><creationdate>20160226</creationdate><title>PIPELINE ADC WITH SHARED GAIN STAGES</title><author>NABIHAH RAZALI ; TAN KONG YEW ; SHARIFAH SALEH ; MOHD. SHAHIMAN SULAIMAN ; ROHAYA ABDUL WAHAB ; YUZMAN YUSOFF ; NAZALIZA OTHMAN ; ROHANA MUSA ; WEE LEONG SON ; HANIF CHE LAH ; HASMAYADI ABDUL MAJID ; ROZAIMAH BAHARIM</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_MY156473A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>NABIHAH RAZALI</creatorcontrib><creatorcontrib>TAN KONG YEW</creatorcontrib><creatorcontrib>SHARIFAH SALEH</creatorcontrib><creatorcontrib>MOHD. SHAHIMAN SULAIMAN</creatorcontrib><creatorcontrib>ROHAYA ABDUL WAHAB</creatorcontrib><creatorcontrib>YUZMAN YUSOFF</creatorcontrib><creatorcontrib>NAZALIZA OTHMAN</creatorcontrib><creatorcontrib>ROHANA MUSA</creatorcontrib><creatorcontrib>WEE LEONG SON</creatorcontrib><creatorcontrib>HANIF CHE LAH</creatorcontrib><creatorcontrib>HASMAYADI ABDUL MAJID</creatorcontrib><creatorcontrib>ROZAIMAH BAHARIM</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NABIHAH RAZALI</au><au>TAN KONG YEW</au><au>SHARIFAH SALEH</au><au>MOHD. SHAHIMAN SULAIMAN</au><au>ROHAYA ABDUL WAHAB</au><au>YUZMAN YUSOFF</au><au>NAZALIZA OTHMAN</au><au>ROHANA MUSA</au><au>WEE LEONG SON</au><au>HANIF CHE LAH</au><au>HASMAYADI ABDUL MAJID</au><au>ROZAIMAH BAHARIM</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PIPELINE ADC WITH SHARED GAIN STAGES</title><date>2016-02-26</date><risdate>2016</risdate><abstract>A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
title PIPELINE ADC WITH SHARED GAIN STAGES
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