PIPELINE ADC WITH SHARED GAIN STAGES
A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDB...
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creator | NABIHAH RAZALI TAN KONG YEW SHARIFAH SALEH MOHD. SHAHIMAN SULAIMAN ROHAYA ABDUL WAHAB YUZMAN YUSOFF NAZALIZA OTHMAN ROHANA MUSA WEE LEONG SON HANIF CHE LAH HASMAYADI ABDUL MAJID ROZAIMAH BAHARIM |
description | A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS: |
format | Patent |
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SHAHIMAN SULAIMAN ; ROHAYA ABDUL WAHAB ; YUZMAN YUSOFF ; NAZALIZA OTHMAN ; ROHANA MUSA ; WEE LEONG SON ; HANIF CHE LAH ; HASMAYADI ABDUL MAJID ; ROZAIMAH BAHARIM</creatorcontrib><description>A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). 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SHAHIMAN SULAIMAN ; ROHAYA ABDUL WAHAB ; YUZMAN YUSOFF ; NAZALIZA OTHMAN ; ROHANA MUSA ; WEE LEONG SON ; HANIF CHE LAH ; HASMAYADI ABDUL MAJID ; ROZAIMAH BAHARIM</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_MY156473A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>NABIHAH RAZALI</creatorcontrib><creatorcontrib>TAN KONG YEW</creatorcontrib><creatorcontrib>SHARIFAH SALEH</creatorcontrib><creatorcontrib>MOHD. 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SHAHIMAN SULAIMAN</au><au>ROHAYA ABDUL WAHAB</au><au>YUZMAN YUSOFF</au><au>NAZALIZA OTHMAN</au><au>ROHANA MUSA</au><au>WEE LEONG SON</au><au>HANIF CHE LAH</au><au>HASMAYADI ABDUL MAJID</au><au>ROZAIMAH BAHARIM</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PIPELINE ADC WITH SHARED GAIN STAGES</title><date>2016-02-26</date><risdate>2016</risdate><abstract>A SHARED GAIN-STAGE CIRCUIT OF A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) THAT ALLOWS FOR SHARING AT LEAST ONE MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) (102) AND AT LEAST ONE SUB-ADC (104) BETWEEN TWO SUCCESSIVE STAGES. THE AT LEAST ONE MDAC (102) COMPRISES AN AMPLIFIER (106), A FIRST FEEDBACK CAPACITOR (108), A SECOND FEEDBACK CAPACITOR (110), AT LEAST TWO SAMPLING CAPACITORS (112), A PLURALITY OF REFERENCE VOLTAGES AND A SUB-DAC (114). THE MOST ILLUSTRATIVE DRAWINGS:</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY |
title | PIPELINE ADC WITH SHARED GAIN STAGES |
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