FABRICATION OF SEMICONDUCTOR DEVICES WITH AIR GAPS FOR ULTRA LOW CAPACITANCE INTERCONNECTIONS AND METHODS OF MAKING SAME

A METHOD OF FORMING AN AIR GAP OR GAPS WITHIN SOLID STRUCTURES AND SPECIFICALLY SEMICONDUCTOR STRUCTURES TO REDUCE CAPACITIVE COUPLING BETWEEN ELECTRICAL ELEMENTS SUCH AS METAL LINES, WHEREIN SACRIFICIAL MATERIAL (20) IS USED TO OCCUPY A CLOSED INTERIOR VOLUME IN A SEMICONDUCTOR STRUCTURE IS DISCLOS...

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Hauptverfasser: CLIFFORD LEE HENDERSON, DHANANJAY M. BHUSARI, SUE ANN BIDSTRUP ALLEN, PAUL ALBERT KOHL, HOLLIE ANNE REED
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creator CLIFFORD LEE HENDERSON
DHANANJAY M. BHUSARI
SUE ANN BIDSTRUP ALLEN
PAUL ALBERT KOHL
HOLLIE ANNE REED
description A METHOD OF FORMING AN AIR GAP OR GAPS WITHIN SOLID STRUCTURES AND SPECIFICALLY SEMICONDUCTOR STRUCTURES TO REDUCE CAPACITIVE COUPLING BETWEEN ELECTRICAL ELEMENTS SUCH AS METAL LINES, WHEREIN SACRIFICIAL MATERIAL (20) IS USED TO OCCUPY A CLOSED INTERIOR VOLUME IN A SEMICONDUCTOR STRUCTURE IS DISCLOSED. THE SACRIFICIAL MATERIAL (20) IS CAUSED TO DECOMPOSE INTO ONE OR MORE GASEOUS DECOMPOSITIOR PRODUCTS WHICH ARE REMOVED, IN ONE EMBODIMENT BY DIFFUSION, THROUGH AN OVERCOAT LAYER (24). TB DECOMPOSITION OF THE SACRIFICIAL MATERIAL (20) LEAVES AN AIR GAP OR GAPS (26) AT THE CLOSED INTERIOI VOLUME PREVIOUSLY OCCUPIED BY THE SACRIFICIAL MATERIAL (20). THE AIR GAPS MAY (26) BE DISPOS& BETWEEN ELECTRICAL LEADS TO MINIMIZE CAPACITIVE COUPLING THEREBETWEEN. ALSO DISCLOSED ARE METHODS OF FORMING MULTI-LEVEL AIR GAPS (26) AND METHODS OF FORMING OVER-COATED CONDUCTIVE LINES OR LEATH WHEREIN A PORTION OF THE OVERCOATING (24) IS IN CONTACT WITH AT LEAST ONE AIR GAP.(FIG 1D)
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_MY128644A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>MY128644A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_MY128644A3</originalsourceid><addsrcrecordid>eNqFjDEOgkAQRWksjHoFMxewUImxHYdZmMjukt1FYkWIWSujJFh4fCGxt3rFf__Nk4_CkxPCINaAVeBZC1mT1RSsg4wvQuyhkVAAioMcKw9qXOoyOITSNkBYIUlAQwxiArvxbpimoAc0GWgOhc38VNd4FpODR83LZHbvHkNc_bhI1ooDFZvYv9o49N0tPuO71dft7nhIU9z_Fb435Ti8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FABRICATION OF SEMICONDUCTOR DEVICES WITH AIR GAPS FOR ULTRA LOW CAPACITANCE INTERCONNECTIONS AND METHODS OF MAKING SAME</title><source>esp@cenet</source><creator>CLIFFORD LEE HENDERSON ; DHANANJAY M. BHUSARI ; SUE ANN BIDSTRUP ALLEN ; PAUL ALBERT KOHL ; HOLLIE ANNE REED</creator><creatorcontrib>CLIFFORD LEE HENDERSON ; DHANANJAY M. BHUSARI ; SUE ANN BIDSTRUP ALLEN ; PAUL ALBERT KOHL ; HOLLIE ANNE REED</creatorcontrib><description>A METHOD OF FORMING AN AIR GAP OR GAPS WITHIN SOLID STRUCTURES AND SPECIFICALLY SEMICONDUCTOR STRUCTURES TO REDUCE CAPACITIVE COUPLING BETWEEN ELECTRICAL ELEMENTS SUCH AS METAL LINES, WHEREIN SACRIFICIAL MATERIAL (20) IS USED TO OCCUPY A CLOSED INTERIOR VOLUME IN A SEMICONDUCTOR STRUCTURE IS DISCLOSED. THE SACRIFICIAL MATERIAL (20) IS CAUSED TO DECOMPOSE INTO ONE OR MORE GASEOUS DECOMPOSITIOR PRODUCTS WHICH ARE REMOVED, IN ONE EMBODIMENT BY DIFFUSION, THROUGH AN OVERCOAT LAYER (24). TB DECOMPOSITION OF THE SACRIFICIAL MATERIAL (20) LEAVES AN AIR GAP OR GAPS (26) AT THE CLOSED INTERIOI VOLUME PREVIOUSLY OCCUPIED BY THE SACRIFICIAL MATERIAL (20). THE AIR GAPS MAY (26) BE DISPOS&amp; BETWEEN ELECTRICAL LEADS TO MINIMIZE CAPACITIVE COUPLING THEREBETWEEN. ALSO DISCLOSED ARE METHODS OF FORMING MULTI-LEVEL AIR GAPS (26) AND METHODS OF FORMING OVER-COATED CONDUCTIVE LINES OR LEATH WHEREIN A PORTION OF THE OVERCOATING (24) IS IN CONTACT WITH AT LEAST ONE AIR GAP.(FIG 1D)</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070228&amp;DB=EPODOC&amp;CC=MY&amp;NR=128644A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070228&amp;DB=EPODOC&amp;CC=MY&amp;NR=128644A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CLIFFORD LEE HENDERSON</creatorcontrib><creatorcontrib>DHANANJAY M. BHUSARI</creatorcontrib><creatorcontrib>SUE ANN BIDSTRUP ALLEN</creatorcontrib><creatorcontrib>PAUL ALBERT KOHL</creatorcontrib><creatorcontrib>HOLLIE ANNE REED</creatorcontrib><title>FABRICATION OF SEMICONDUCTOR DEVICES WITH AIR GAPS FOR ULTRA LOW CAPACITANCE INTERCONNECTIONS AND METHODS OF MAKING SAME</title><description>A METHOD OF FORMING AN AIR GAP OR GAPS WITHIN SOLID STRUCTURES AND SPECIFICALLY SEMICONDUCTOR STRUCTURES TO REDUCE CAPACITIVE COUPLING BETWEEN ELECTRICAL ELEMENTS SUCH AS METAL LINES, WHEREIN SACRIFICIAL MATERIAL (20) IS USED TO OCCUPY A CLOSED INTERIOR VOLUME IN A SEMICONDUCTOR STRUCTURE IS DISCLOSED. THE SACRIFICIAL MATERIAL (20) IS CAUSED TO DECOMPOSE INTO ONE OR MORE GASEOUS DECOMPOSITIOR PRODUCTS WHICH ARE REMOVED, IN ONE EMBODIMENT BY DIFFUSION, THROUGH AN OVERCOAT LAYER (24). TB DECOMPOSITION OF THE SACRIFICIAL MATERIAL (20) LEAVES AN AIR GAP OR GAPS (26) AT THE CLOSED INTERIOI VOLUME PREVIOUSLY OCCUPIED BY THE SACRIFICIAL MATERIAL (20). THE AIR GAPS MAY (26) BE DISPOS&amp; BETWEEN ELECTRICAL LEADS TO MINIMIZE CAPACITIVE COUPLING THEREBETWEEN. ALSO DISCLOSED ARE METHODS OF FORMING MULTI-LEVEL AIR GAPS (26) AND METHODS OF FORMING OVER-COATED CONDUCTIVE LINES OR LEATH WHEREIN A PORTION OF THE OVERCOATING (24) IS IN CONTACT WITH AT LEAST ONE AIR GAP.(FIG 1D)</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFjDEOgkAQRWksjHoFMxewUImxHYdZmMjukt1FYkWIWSujJFh4fCGxt3rFf__Nk4_CkxPCINaAVeBZC1mT1RSsg4wvQuyhkVAAioMcKw9qXOoyOITSNkBYIUlAQwxiArvxbpimoAc0GWgOhc38VNd4FpODR83LZHbvHkNc_bhI1ooDFZvYv9o49N0tPuO71dft7nhIU9z_Fb435Ti8</recordid><startdate>20070228</startdate><enddate>20070228</enddate><creator>CLIFFORD LEE HENDERSON</creator><creator>DHANANJAY M. BHUSARI</creator><creator>SUE ANN BIDSTRUP ALLEN</creator><creator>PAUL ALBERT KOHL</creator><creator>HOLLIE ANNE REED</creator><scope>EVB</scope></search><sort><creationdate>20070228</creationdate><title>FABRICATION OF SEMICONDUCTOR DEVICES WITH AIR GAPS FOR ULTRA LOW CAPACITANCE INTERCONNECTIONS AND METHODS OF MAKING SAME</title><author>CLIFFORD LEE HENDERSON ; DHANANJAY M. BHUSARI ; SUE ANN BIDSTRUP ALLEN ; PAUL ALBERT KOHL ; HOLLIE ANNE REED</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_MY128644A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CLIFFORD LEE HENDERSON</creatorcontrib><creatorcontrib>DHANANJAY M. BHUSARI</creatorcontrib><creatorcontrib>SUE ANN BIDSTRUP ALLEN</creatorcontrib><creatorcontrib>PAUL ALBERT KOHL</creatorcontrib><creatorcontrib>HOLLIE ANNE REED</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CLIFFORD LEE HENDERSON</au><au>DHANANJAY M. BHUSARI</au><au>SUE ANN BIDSTRUP ALLEN</au><au>PAUL ALBERT KOHL</au><au>HOLLIE ANNE REED</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FABRICATION OF SEMICONDUCTOR DEVICES WITH AIR GAPS FOR ULTRA LOW CAPACITANCE INTERCONNECTIONS AND METHODS OF MAKING SAME</title><date>2007-02-28</date><risdate>2007</risdate><abstract>A METHOD OF FORMING AN AIR GAP OR GAPS WITHIN SOLID STRUCTURES AND SPECIFICALLY SEMICONDUCTOR STRUCTURES TO REDUCE CAPACITIVE COUPLING BETWEEN ELECTRICAL ELEMENTS SUCH AS METAL LINES, WHEREIN SACRIFICIAL MATERIAL (20) IS USED TO OCCUPY A CLOSED INTERIOR VOLUME IN A SEMICONDUCTOR STRUCTURE IS DISCLOSED. THE SACRIFICIAL MATERIAL (20) IS CAUSED TO DECOMPOSE INTO ONE OR MORE GASEOUS DECOMPOSITIOR PRODUCTS WHICH ARE REMOVED, IN ONE EMBODIMENT BY DIFFUSION, THROUGH AN OVERCOAT LAYER (24). TB DECOMPOSITION OF THE SACRIFICIAL MATERIAL (20) LEAVES AN AIR GAP OR GAPS (26) AT THE CLOSED INTERIOI VOLUME PREVIOUSLY OCCUPIED BY THE SACRIFICIAL MATERIAL (20). THE AIR GAPS MAY (26) BE DISPOS&amp; BETWEEN ELECTRICAL LEADS TO MINIMIZE CAPACITIVE COUPLING THEREBETWEEN. ALSO DISCLOSED ARE METHODS OF FORMING MULTI-LEVEL AIR GAPS (26) AND METHODS OF FORMING OVER-COATED CONDUCTIVE LINES OR LEATH WHEREIN A PORTION OF THE OVERCOATING (24) IS IN CONTACT WITH AT LEAST ONE AIR GAP.(FIG 1D)</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title FABRICATION OF SEMICONDUCTOR DEVICES WITH AIR GAPS FOR ULTRA LOW CAPACITANCE INTERCONNECTIONS AND METHODS OF MAKING SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T13%3A54%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CLIFFORD%20LEE%20HENDERSON&rft.date=2007-02-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EMY128644A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true