A MICROCONTROLLER INCLUDING A SINGLE MEMORY MODULE HAVING A DATA MEMORY SECTOR AND A CODE MEMORY SECTOR AND SUPPORTING SIMULATENOUS READ/WRITE ACCESS TO BOTH SECTORS
A MICROCONTROLLER (1) HAVING A SPECIAL FUNCTION REGISTER TO INTERNALLY SELECT BETWEEN INTERNAL MEMORY (35) AND EXTERNAL MEMORY ON THE FLY. TWO DATA POINTERS (41,43) IN CONJUNCTION WITH THE SPECIAL FUNCTION REGISTER RESULT IN FOUR EFFECTIVE QUICK REFERENCE LOCATIONS. THE INTERNAL MEMORY CONSISTS OF O...
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creator | TSUNG D. MOK DUNCAN CURRY ARTHUR Y. YU |
description | A MICROCONTROLLER (1) HAVING A SPECIAL FUNCTION REGISTER TO INTERNALLY SELECT BETWEEN INTERNAL MEMORY (35) AND EXTERNAL MEMORY ON THE FLY. TWO DATA POINTERS (41,43) IN CONJUNCTION WITH THE SPECIAL FUNCTION REGISTER RESULT IN FOUR EFFECTIVE QUICK REFERENCE LOCATIONS. THE INTERNAL MEMORY CONSISTS OF ONE MEMORY MODULE HAVING ITS ARRAY (66) SUBDIVIDED INTO A DATA MEMORY STORE AND A CODE MEMORY STORE, AND HAVING A BANK OF PASS DEVICES (73) TO SELECTIVELY ISOLATE THE CODE MEMORY STORE FROM THE DATA MEMORY STORE. THE PRESENT MEMORY CAN FURTHER SUPPORT CONCURRENT WRITING TO THE DATA MEMORY STORE WHILE READING FROM THE CODE MEMORY STORE. THIS IS DONE THROUGH ONE OF TWO MEMORY EMBODIMENTS. IN A FIRST MEMORY EMBODIMENT TWO Y-DECODERS ARE USED; A FIRST Y-DECODER ADJACENT THE CODE MEMORY STORE AND A SECOND Y-DECODER ADJACENT THE DATA MEMORY STORE. WHEN A SIMULTANEOUS READ/WRITE INSTRUCTION IS STARTED, THE OUTPUTS FROM THE SECOND Y-DECODER (96) AND AN X-DECODER (95) ARE LATCHED. THE LATCHES MAINTAIN ACTIVE THE SELECTED MEMORY LOCATION WITHIN THE DATA MEMORY STORE WHILE THE BANK OF PASS DEVICES ISOLATE IT FROM THE CODE MEMORY STORED. IN A SECOND EMBODIMENT, THE SECOND Y-DECODER IS REPLACED WITH A HIGH VOLTAGE PAGE. THE HIGH VOLTAGE PAGE SUPPLIES PROGRAM AND ERASE VOLTAGES DIRECTLY TO THE DATA MEMORY STORE AND INDIRECTLY THROUGH THE BANK OF PASS DEVICES (73) TO THE CODE MEMORY STORE. FIGURE 1 |
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YU</creatorcontrib><description>A MICROCONTROLLER (1) HAVING A SPECIAL FUNCTION REGISTER TO INTERNALLY SELECT BETWEEN INTERNAL MEMORY (35) AND EXTERNAL MEMORY ON THE FLY. TWO DATA POINTERS (41,43) IN CONJUNCTION WITH THE SPECIAL FUNCTION REGISTER RESULT IN FOUR EFFECTIVE QUICK REFERENCE LOCATIONS. THE INTERNAL MEMORY CONSISTS OF ONE MEMORY MODULE HAVING ITS ARRAY (66) SUBDIVIDED INTO A DATA MEMORY STORE AND A CODE MEMORY STORE, AND HAVING A BANK OF PASS DEVICES (73) TO SELECTIVELY ISOLATE THE CODE MEMORY STORE FROM THE DATA MEMORY STORE. THE PRESENT MEMORY CAN FURTHER SUPPORT CONCURRENT WRITING TO THE DATA MEMORY STORE WHILE READING FROM THE CODE MEMORY STORE. THIS IS DONE THROUGH ONE OF TWO MEMORY EMBODIMENTS. IN A FIRST MEMORY EMBODIMENT TWO Y-DECODERS ARE USED; A FIRST Y-DECODER ADJACENT THE CODE MEMORY STORE AND A SECOND Y-DECODER ADJACENT THE DATA MEMORY STORE. WHEN A SIMULTANEOUS READ/WRITE INSTRUCTION IS STARTED, THE OUTPUTS FROM THE SECOND Y-DECODER (96) AND AN X-DECODER (95) ARE LATCHED. THE LATCHES MAINTAIN ACTIVE THE SELECTED MEMORY LOCATION WITHIN THE DATA MEMORY STORE WHILE THE BANK OF PASS DEVICES ISOLATE IT FROM THE CODE MEMORY STORED. IN A SECOND EMBODIMENT, THE SECOND Y-DECODER IS REPLACED WITH A HIGH VOLTAGE PAGE. THE HIGH VOLTAGE PAGE SUPPLIES PROGRAM AND ERASE VOLTAGES DIRECTLY TO THE DATA MEMORY STORE AND INDIRECTLY THROUGH THE BANK OF PASS DEVICES (73) TO THE CODE MEMORY STORE. FIGURE 1</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021130&DB=EPODOC&CC=MY&NR=114633A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021130&DB=EPODOC&CC=MY&NR=114633A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TSUNG D. MOK</creatorcontrib><creatorcontrib>DUNCAN CURRY</creatorcontrib><creatorcontrib>ARTHUR Y. YU</creatorcontrib><title>A MICROCONTROLLER INCLUDING A SINGLE MEMORY MODULE HAVING A DATA MEMORY SECTOR AND A CODE MEMORY SECTOR AND SUPPORTING SIMULATENOUS READ/WRITE ACCESS TO BOTH SECTORS</title><description>A MICROCONTROLLER (1) HAVING A SPECIAL FUNCTION REGISTER TO INTERNALLY SELECT BETWEEN INTERNAL MEMORY (35) AND EXTERNAL MEMORY ON THE FLY. TWO DATA POINTERS (41,43) IN CONJUNCTION WITH THE SPECIAL FUNCTION REGISTER RESULT IN FOUR EFFECTIVE QUICK REFERENCE LOCATIONS. THE INTERNAL MEMORY CONSISTS OF ONE MEMORY MODULE HAVING ITS ARRAY (66) SUBDIVIDED INTO A DATA MEMORY STORE AND A CODE MEMORY STORE, AND HAVING A BANK OF PASS DEVICES (73) TO SELECTIVELY ISOLATE THE CODE MEMORY STORE FROM THE DATA MEMORY STORE. THE PRESENT MEMORY CAN FURTHER SUPPORT CONCURRENT WRITING TO THE DATA MEMORY STORE WHILE READING FROM THE CODE MEMORY STORE. THIS IS DONE THROUGH ONE OF TWO MEMORY EMBODIMENTS. IN A FIRST MEMORY EMBODIMENT TWO Y-DECODERS ARE USED; A FIRST Y-DECODER ADJACENT THE CODE MEMORY STORE AND A SECOND Y-DECODER ADJACENT THE DATA MEMORY STORE. WHEN A SIMULTANEOUS READ/WRITE INSTRUCTION IS STARTED, THE OUTPUTS FROM THE SECOND Y-DECODER (96) AND AN X-DECODER (95) ARE LATCHED. THE LATCHES MAINTAIN ACTIVE THE SELECTED MEMORY LOCATION WITHIN THE DATA MEMORY STORE WHILE THE BANK OF PASS DEVICES ISOLATE IT FROM THE CODE MEMORY STORED. IN A SECOND EMBODIMENT, THE SECOND Y-DECODER IS REPLACED WITH A HIGH VOLTAGE PAGE. THE HIGH VOLTAGE PAGE SUPPLIES PROGRAM AND ERASE VOLTAGES DIRECTLY TO THE DATA MEMORY STORE AND INDIRECTLY THROUGH THE BANK OF PASS DEVICES (73) TO THE CODE MEMORY STORE. FIGURE 1</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFi0EKwjAQRbtxIeoVZC4gUirux2S0gSQjyUTpqojElahQr-Q9rag7wdXj8_4bFg8EZ1RgxV4CW0sBjFc2aeM3gBB7WAJHjkMDjnXqV427t9Uo-HWRlHAA9LoXijX9EDFttxzkFUfjkkUhzylCINTzfTBCgEpRjCAMK5b6E8dxMTgdzl2efDgqpmsSVc_y7drm7nY45ku-t64py8WyqrD6e3gCIbhFHQ</recordid><startdate>20021130</startdate><enddate>20021130</enddate><creator>TSUNG D. MOK</creator><creator>DUNCAN CURRY</creator><creator>ARTHUR Y. YU</creator><scope>EVB</scope></search><sort><creationdate>20021130</creationdate><title>A MICROCONTROLLER INCLUDING A SINGLE MEMORY MODULE HAVING A DATA MEMORY SECTOR AND A CODE MEMORY SECTOR AND SUPPORTING SIMULATENOUS READ/WRITE ACCESS TO BOTH SECTORS</title><author>TSUNG D. MOK ; DUNCAN CURRY ; ARTHUR Y. YU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_MY114633A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>TSUNG D. MOK</creatorcontrib><creatorcontrib>DUNCAN CURRY</creatorcontrib><creatorcontrib>ARTHUR Y. YU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TSUNG D. MOK</au><au>DUNCAN CURRY</au><au>ARTHUR Y. YU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A MICROCONTROLLER INCLUDING A SINGLE MEMORY MODULE HAVING A DATA MEMORY SECTOR AND A CODE MEMORY SECTOR AND SUPPORTING SIMULATENOUS READ/WRITE ACCESS TO BOTH SECTORS</title><date>2002-11-30</date><risdate>2002</risdate><abstract>A MICROCONTROLLER (1) HAVING A SPECIAL FUNCTION REGISTER TO INTERNALLY SELECT BETWEEN INTERNAL MEMORY (35) AND EXTERNAL MEMORY ON THE FLY. TWO DATA POINTERS (41,43) IN CONJUNCTION WITH THE SPECIAL FUNCTION REGISTER RESULT IN FOUR EFFECTIVE QUICK REFERENCE LOCATIONS. THE INTERNAL MEMORY CONSISTS OF ONE MEMORY MODULE HAVING ITS ARRAY (66) SUBDIVIDED INTO A DATA MEMORY STORE AND A CODE MEMORY STORE, AND HAVING A BANK OF PASS DEVICES (73) TO SELECTIVELY ISOLATE THE CODE MEMORY STORE FROM THE DATA MEMORY STORE. THE PRESENT MEMORY CAN FURTHER SUPPORT CONCURRENT WRITING TO THE DATA MEMORY STORE WHILE READING FROM THE CODE MEMORY STORE. THIS IS DONE THROUGH ONE OF TWO MEMORY EMBODIMENTS. IN A FIRST MEMORY EMBODIMENT TWO Y-DECODERS ARE USED; A FIRST Y-DECODER ADJACENT THE CODE MEMORY STORE AND A SECOND Y-DECODER ADJACENT THE DATA MEMORY STORE. WHEN A SIMULTANEOUS READ/WRITE INSTRUCTION IS STARTED, THE OUTPUTS FROM THE SECOND Y-DECODER (96) AND AN X-DECODER (95) ARE LATCHED. THE LATCHES MAINTAIN ACTIVE THE SELECTED MEMORY LOCATION WITHIN THE DATA MEMORY STORE WHILE THE BANK OF PASS DEVICES ISOLATE IT FROM THE CODE MEMORY STORED. IN A SECOND EMBODIMENT, THE SECOND Y-DECODER IS REPLACED WITH A HIGH VOLTAGE PAGE. THE HIGH VOLTAGE PAGE SUPPLIES PROGRAM AND ERASE VOLTAGES DIRECTLY TO THE DATA MEMORY STORE AND INDIRECTLY THROUGH THE BANK OF PASS DEVICES (73) TO THE CODE MEMORY STORE. FIGURE 1</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
title | A MICROCONTROLLER INCLUDING A SINGLE MEMORY MODULE HAVING A DATA MEMORY SECTOR AND A CODE MEMORY SECTOR AND SUPPORTING SIMULATENOUS READ/WRITE ACCESS TO BOTH SECTORS |
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