SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EMPLOYING MOSFETS
A semiconductor integrated circuit device which enables the relaxation of deterioration in reliability due to the hot electron effect and a further promotion of high integration density is disclosed. For this purpose, a MOSFET having a drain region consisting of a low concentration impurity diffused...
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creator | KOSHIMARU, SHIGERU |
description | A semiconductor integrated circuit device which enables the relaxation of deterioration in reliability due to the hot electron effect and a further promotion of high integration density is disclosed. For this purpose, a MOSFET having a drain region consisting of a low concentration impurity diffused layer and a high concentration impurity diffused layer with shallow junction is employed. The variations of the device characteristics are averaged out and the life of the device as a whole is prolonged by increasing the length of the low concentration impurity diffused layer of an N-channel MOSFET, of a circuit whose operating conditions are susceptible to the hot electron effect as in the case of a CMOS address inverter which receives an address signal supplied as a TTL output, and by lowering the drain voltage by an advantageous use of the potential drop due to the resistance of the low concentration impurity diffused layer. The length of the low concentration impurity diffused layer of other MOSFETs is designed by considering the withstand voltage against punch-through between the drain and the source. In this way, it becomes possible to reduce the channel length compared with the case of a device with LDD structure. |
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For this purpose, a MOSFET having a drain region consisting of a low concentration impurity diffused layer and a high concentration impurity diffused layer with shallow junction is employed. The variations of the device characteristics are averaged out and the life of the device as a whole is prolonged by increasing the length of the low concentration impurity diffused layer of an N-channel MOSFET, of a circuit whose operating conditions are susceptible to the hot electron effect as in the case of a CMOS address inverter which receives an address signal supplied as a TTL output, and by lowering the drain voltage by an advantageous use of the potential drop due to the resistance of the low concentration impurity diffused layer. The length of the low concentration impurity diffused layer of other MOSFETs is designed by considering the withstand voltage against punch-through between the drain and the source. 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For this purpose, a MOSFET having a drain region consisting of a low concentration impurity diffused layer and a high concentration impurity diffused layer with shallow junction is employed. The variations of the device characteristics are averaged out and the life of the device as a whole is prolonged by increasing the length of the low concentration impurity diffused layer of an N-channel MOSFET, of a circuit whose operating conditions are susceptible to the hot electron effect as in the case of a CMOS address inverter which receives an address signal supplied as a TTL output, and by lowering the drain voltage by an advantageous use of the potential drop due to the resistance of the low concentration impurity diffused layer. The length of the low concentration impurity diffused layer of other MOSFETs is designed by considering the withstand voltage against punch-through between the drain and the source. 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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE EMPLOYING MOSFETS |
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