TEST SYSTEM THAT PERFORMS A TEST MODE FOR A PLURALITY OF MEMORY DEVICES

TEST SYSTEM THAT PERFORMS A TEST MODE FOR A PLURALITY OF MEMORY DEVICES

테스트시스템은 테스트모드를 수행하기 위한 커맨드어드레스 및 테스트클럭을 출력하고, 비교신호를 수신하는 테스트장치 및 상기 커맨드어드레스를 토대로 상기 테스트모드에 진입하고, 상기 커맨드어드레스에 의해 초기값을 설정하며, 프리차지동작 시 상기 커맨드어드레스의 로직레벨 조합에 따라 상기 초기값에 대한 연산동작을 수행하여 로우어드레스 및 컬럼어드레스를 생성하며, 상기 로우어드레스 및 상기 컬럼어드레스를 토대로 출력되는 내부데이터를 압축 및 비교하여 상기 비교신호로 출력하는 메모리장치를 포함한다. A test system includes...

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Hauptverfasser: JEONG BONG HWA, SEO YONG HO, JUNG WOO SIK, LEE JUN PHYO, HYUN SANG AH
Format: Patent
Sprache:eng ; kor
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator JEONG BONG HWA
SEO YONG HO
JUNG WOO SIK
LEE JUN PHYO
HYUN SANG AH
description 테스트시스템은 테스트모드를 수행하기 위한 커맨드어드레스 및 테스트클럭을 출력하고, 비교신호를 수신하는 테스트장치 및 상기 커맨드어드레스를 토대로 상기 테스트모드에 진입하고, 상기 커맨드어드레스에 의해 초기값을 설정하며, 프리차지동작 시 상기 커맨드어드레스의 로직레벨 조합에 따라 상기 초기값에 대한 연산동작을 수행하여 로우어드레스 및 컬럼어드레스를 생성하며, 상기 로우어드레스 및 상기 컬럼어드레스를 토대로 출력되는 내부데이터를 압축 및 비교하여 상기 비교신호로 출력하는 메모리장치를 포함한다. A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.
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A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAPcQ0OUQiODA5x9VUI8XAMUQhwDXLzD_INVnBUAMv5-ru4KgBFgPwAn9AgRx_PkEgFfzcFX1df_6BIBRfXME9n12AeBta0xJziVF4ozc2g7OYa4uyhm1qQH59aXJCYnJqXWhLvHWRkYGRiYGBmaWxu7mhMnCoAgkEtYw</recordid><startdate>20240520</startdate><enddate>20240520</enddate><creator>JEONG BONG HWA</creator><creator>SEO YONG HO</creator><creator>JUNG WOO SIK</creator><creator>LEE JUN PHYO</creator><creator>HYUN SANG AH</creator><scope>EVB</scope></search><sort><creationdate>20240520</creationdate><title>TEST SYSTEM THAT PERFORMS A TEST MODE FOR A PLURALITY OF MEMORY DEVICES</title><author>JEONG BONG HWA ; SEO YONG HO ; JUNG WOO SIK ; LEE JUN PHYO ; HYUN SANG AH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20240069377A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2024</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>JEONG BONG HWA</creatorcontrib><creatorcontrib>SEO YONG HO</creatorcontrib><creatorcontrib>JUNG WOO SIK</creatorcontrib><creatorcontrib>LEE JUN PHYO</creatorcontrib><creatorcontrib>HYUN SANG AH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEONG BONG HWA</au><au>SEO YONG HO</au><au>JUNG WOO SIK</au><au>LEE JUN PHYO</au><au>HYUN SANG AH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TEST SYSTEM THAT PERFORMS A TEST MODE FOR A PLURALITY OF MEMORY DEVICES</title><date>2024-05-20</date><risdate>2024</risdate><abstract>테스트시스템은 테스트모드를 수행하기 위한 커맨드어드레스 및 테스트클럭을 출력하고, 비교신호를 수신하는 테스트장치 및 상기 커맨드어드레스를 토대로 상기 테스트모드에 진입하고, 상기 커맨드어드레스에 의해 초기값을 설정하며, 프리차지동작 시 상기 커맨드어드레스의 로직레벨 조합에 따라 상기 초기값에 대한 연산동작을 수행하여 로우어드레스 및 컬럼어드레스를 생성하며, 상기 로우어드레스 및 상기 컬럼어드레스를 토대로 출력되는 내부데이터를 압축 및 비교하여 상기 비교신호로 출력하는 메모리장치를 포함한다. A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.</abstract><oa>free_for_read</oa></addata></record>
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title TEST SYSTEM THAT PERFORMS A TEST MODE FOR A PLURALITY OF MEMORY DEVICES
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