Power semiconductor device power semiconductor chip including the same and method for manufacturing the same
A power semiconductor device according to one embodiment of the present invention may comprise: gate electrodes which are arranged to be recessed from a first surface of a semiconductor substrate towards a second surface facing the first surface, respectively; an emitter area which is arranged to be...
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creator | YUN SEONG HWAN WOO HYUK PARK TAE YOUNG LEE JU HWAN JO SEON HYEONG KANG MIN GI KIM TAE YANG |
description | A power semiconductor device according to one embodiment of the present invention may comprise: gate electrodes which are arranged to be recessed from a first surface of a semiconductor substrate towards a second surface facing the first surface, respectively; an emitter area which is arranged to be in contact with each of a trench having the gate electrode arranged, and the first surface, and contains a first conductive type impurity; a collector area which is arranged to be in contact with the second surface and contains a second conductive type impurity, an opposite conductive type of the first conductive type; a floating area which is extended towards the second surface in an extension direction of the trench while surrounding a bottom surface of the trench and contains the second conductive type impurity; and a trench emitter area which is arranged between the gate electrodes in the trench. According to the present invention, the power semiconductor device can improve operational stability while securing withstand voltage characteristics against high voltages.
본 발명의 일 실시예에 따른 전력 반도체 소자는, 각각이 반도체 기판의 제1 면으로부터 상기 제1 면에 대향하는 제2 면을 향해 리세스(recess) 되도록 배치되는 게이트 전극들, 상기 게이트 전극이 배치되는 트렌치 및 상기 제1 면 각각에 접하도록 배치되고, 제1 도전형의 불순물을 포함하는 이미터 영역, 상기 제2 면에 접하도록 배치되고, 상기 제1 도전형의 반대 도전형인 제2 도전형의 불순물을 포함하는 콜렉터 영역, 상기 트렌치의 바닥면을 감싸면서 상기 트렌치의 신장 방향을 따라 상기 제2 면을 향해 신장되고, 상기 제2 도전형의 불순물을 포함하는 플로팅 영역, 및 상기 트렌치 내에서 상기 게이트 전극들 사이에 배치되는 트렌치 이미터 영역을 포함할 수 있다. |
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본 발명의 일 실시예에 따른 전력 반도체 소자는, 각각이 반도체 기판의 제1 면으로부터 상기 제1 면에 대향하는 제2 면을 향해 리세스(recess) 되도록 배치되는 게이트 전극들, 상기 게이트 전극이 배치되는 트렌치 및 상기 제1 면 각각에 접하도록 배치되고, 제1 도전형의 불순물을 포함하는 이미터 영역, 상기 제2 면에 접하도록 배치되고, 상기 제1 도전형의 반대 도전형인 제2 도전형의 불순물을 포함하는 콜렉터 영역, 상기 트렌치의 바닥면을 감싸면서 상기 트렌치의 신장 방향을 따라 상기 제2 면을 향해 신장되고, 상기 제2 도전형의 불순물을 포함하는 플로팅 영역, 및 상기 트렌치 내에서 상기 게이트 전극들 사이에 배치되는 트렌치 이미터 영역을 포함할 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231101&DB=EPODOC&CC=KR&NR=20230151276A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25553,76306</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20231101&DB=EPODOC&CC=KR&NR=20230151276A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YUN SEONG HWAN</creatorcontrib><creatorcontrib>WOO HYUK</creatorcontrib><creatorcontrib>PARK TAE YOUNG</creatorcontrib><creatorcontrib>LEE JU HWAN</creatorcontrib><creatorcontrib>JO SEON HYEONG</creatorcontrib><creatorcontrib>KANG MIN GI</creatorcontrib><creatorcontrib>KIM TAE YANG</creatorcontrib><title>Power semiconductor device power semiconductor chip including the same and method for manufacturing the same</title><description>A power semiconductor device according to one embodiment of the present invention may comprise: gate electrodes which are arranged to be recessed from a first surface of a semiconductor substrate towards a second surface facing the first surface, respectively; an emitter area which is arranged to be in contact with each of a trench having the gate electrode arranged, and the first surface, and contains a first conductive type impurity; a collector area which is arranged to be in contact with the second surface and contains a second conductive type impurity, an opposite conductive type of the first conductive type; a floating area which is extended towards the second surface in an extension direction of the trench while surrounding a bottom surface of the trench and contains the second conductive type impurity; and a trench emitter area which is arranged between the gate electrodes in the trench. According to the present invention, the power semiconductor device can improve operational stability while securing withstand voltage characteristics against high voltages.
본 발명의 일 실시예에 따른 전력 반도체 소자는, 각각이 반도체 기판의 제1 면으로부터 상기 제1 면에 대향하는 제2 면을 향해 리세스(recess) 되도록 배치되는 게이트 전극들, 상기 게이트 전극이 배치되는 트렌치 및 상기 제1 면 각각에 접하도록 배치되고, 제1 도전형의 불순물을 포함하는 이미터 영역, 상기 제2 면에 접하도록 배치되고, 상기 제1 도전형의 반대 도전형인 제2 도전형의 불순물을 포함하는 콜렉터 영역, 상기 트렌치의 바닥면을 감싸면서 상기 트렌치의 신장 방향을 따라 상기 제2 면을 향해 신장되고, 상기 제2 도전형의 불순물을 포함하는 플로팅 영역, 및 상기 트렌치 내에서 상기 게이트 전극들 사이에 배치되는 트렌치 이미터 영역을 포함할 수 있다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrsKAjEQQNE0FqL-w4C1sJtFrUUUwUbEfgmTiQkkk5CH_r4WFhYWVre4Zyr8JT4pQ6HgMLJuWGMGTQ-HBOnHQusSOEbftOM7VEtQVCBQrCFQtVGDebOguBmFteVvNRcTo3yhxaczsTwebvvTilIcqSSFxFTH81V2cuj6dS-3m93wn3oBkYRDLw</recordid><startdate>20231101</startdate><enddate>20231101</enddate><creator>YUN SEONG HWAN</creator><creator>WOO HYUK</creator><creator>PARK TAE YOUNG</creator><creator>LEE JU HWAN</creator><creator>JO SEON HYEONG</creator><creator>KANG MIN GI</creator><creator>KIM TAE YANG</creator><scope>EVB</scope></search><sort><creationdate>20231101</creationdate><title>Power semiconductor device power semiconductor chip including the same and method for manufacturing the same</title><author>YUN SEONG HWAN ; WOO HYUK ; PARK TAE YOUNG ; LEE JU HWAN ; JO SEON HYEONG ; KANG MIN GI ; KIM TAE YANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20230151276A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YUN SEONG HWAN</creatorcontrib><creatorcontrib>WOO HYUK</creatorcontrib><creatorcontrib>PARK TAE YOUNG</creatorcontrib><creatorcontrib>LEE JU HWAN</creatorcontrib><creatorcontrib>JO SEON HYEONG</creatorcontrib><creatorcontrib>KANG MIN GI</creatorcontrib><creatorcontrib>KIM TAE YANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YUN SEONG HWAN</au><au>WOO HYUK</au><au>PARK TAE YOUNG</au><au>LEE JU HWAN</au><au>JO SEON HYEONG</au><au>KANG MIN GI</au><au>KIM TAE YANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power semiconductor device power semiconductor chip including the same and method for manufacturing the same</title><date>2023-11-01</date><risdate>2023</risdate><abstract>A power semiconductor device according to one embodiment of the present invention may comprise: gate electrodes which are arranged to be recessed from a first surface of a semiconductor substrate towards a second surface facing the first surface, respectively; an emitter area which is arranged to be in contact with each of a trench having the gate electrode arranged, and the first surface, and contains a first conductive type impurity; a collector area which is arranged to be in contact with the second surface and contains a second conductive type impurity, an opposite conductive type of the first conductive type; a floating area which is extended towards the second surface in an extension direction of the trench while surrounding a bottom surface of the trench and contains the second conductive type impurity; and a trench emitter area which is arranged between the gate electrodes in the trench. According to the present invention, the power semiconductor device can improve operational stability while securing withstand voltage characteristics against high voltages.
본 발명의 일 실시예에 따른 전력 반도체 소자는, 각각이 반도체 기판의 제1 면으로부터 상기 제1 면에 대향하는 제2 면을 향해 리세스(recess) 되도록 배치되는 게이트 전극들, 상기 게이트 전극이 배치되는 트렌치 및 상기 제1 면 각각에 접하도록 배치되고, 제1 도전형의 불순물을 포함하는 이미터 영역, 상기 제2 면에 접하도록 배치되고, 상기 제1 도전형의 반대 도전형인 제2 도전형의 불순물을 포함하는 콜렉터 영역, 상기 트렌치의 바닥면을 감싸면서 상기 트렌치의 신장 방향을 따라 상기 제2 면을 향해 신장되고, 상기 제2 도전형의 불순물을 포함하는 플로팅 영역, 및 상기 트렌치 내에서 상기 게이트 전극들 사이에 배치되는 트렌치 이미터 영역을 포함할 수 있다.</abstract><oa>free_for_read</oa></addata></record> |
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title | Power semiconductor device power semiconductor chip including the same and method for manufacturing the same |
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