BUFFER CIRCUIT CAPABLE OF REDUCING NOISE
A buffer circuit may comprise: a power control circuit; an inverting circuit; and a voltage adjustment circuit. The power control circuit provides a voltage based on an input signal and a mode signal, and the inverting circuit may generate an output signal by input-receiving and inverting the voltag...
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| creator | JUN SEO JANG JAE HYEONG HONG JIN HA HWANG SOON SUNG AN |
| description | A buffer circuit may comprise: a power control circuit; an inverting circuit; and a voltage adjustment circuit. The power control circuit provides a voltage based on an input signal and a mode signal, and the inverting circuit may generate an output signal by input-receiving and inverting the voltage. The voltage adjustment circuit may adjust a voltage level based on the mode signal and the output signal. Therefore, the present invention is capable of improving a performance.
버퍼 회로는, 전원 제어 회로 및 인버팅 회로, 전압 조절 회로를 포함할 수 있다. 상기 전원 제어 회로는 입력 신호 및 모드 신호에 기초하여 전압을 제공하고, 상기 인버팅 회로는 전압을 입력 받아 반전하여 출력 신호를 생성할 수 있다. 상기 전압 조절 회로는 모드 신호 및 출력 신호에 기초하여 전압 레벨을 조절할 수 있다. |
| format | Patent |
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버퍼 회로는, 전원 제어 회로 및 인버팅 회로, 전압 조절 회로를 포함할 수 있다. 상기 전원 제어 회로는 입력 신호 및 모드 신호에 기초하여 전압을 제공하고, 상기 인버팅 회로는 전압을 입력 받아 반전하여 출력 신호를 생성할 수 있다. 상기 전압 조절 회로는 모드 신호 및 출력 신호에 기초하여 전압 레벨을 조절할 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230102&DB=EPODOC&CC=KR&NR=20230000077A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230102&DB=EPODOC&CC=KR&NR=20230000077A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JUN SEO JANG</creatorcontrib><creatorcontrib>JAE HYEONG HONG</creatorcontrib><creatorcontrib>JIN HA HWANG</creatorcontrib><creatorcontrib>SOON SUNG AN</creatorcontrib><title>BUFFER CIRCUIT CAPABLE OF REDUCING NOISE</title><description>A buffer circuit may comprise: a power control circuit; an inverting circuit; and a voltage adjustment circuit. The power control circuit provides a voltage based on an input signal and a mode signal, and the inverting circuit may generate an output signal by input-receiving and inverting the voltage. The voltage adjustment circuit may adjust a voltage level based on the mode signal and the output signal. Therefore, the present invention is capable of improving a performance.
버퍼 회로는, 전원 제어 회로 및 인버팅 회로, 전압 조절 회로를 포함할 수 있다. 상기 전원 제어 회로는 입력 신호 및 모드 신호에 기초하여 전압을 제공하고, 상기 인버팅 회로는 전압을 입력 받아 반전하여 출력 신호를 생성할 수 있다. 상기 전압 조절 회로는 모드 신호 및 출력 신호에 기초하여 전압 레벨을 조절할 수 있다.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBwCnVzcw1ScPYMcg71DFFwdgxwdPJxVfB3UwhydQl19vRzV_Dz9wx25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgZGxgYgYG7uaEycKgByhySO</recordid><startdate>20230102</startdate><enddate>20230102</enddate><creator>JUN SEO JANG</creator><creator>JAE HYEONG HONG</creator><creator>JIN HA HWANG</creator><creator>SOON SUNG AN</creator><scope>EVB</scope></search><sort><creationdate>20230102</creationdate><title>BUFFER CIRCUIT CAPABLE OF REDUCING NOISE</title><author>JUN SEO JANG ; JAE HYEONG HONG ; JIN HA HWANG ; SOON SUNG AN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20230000077A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2023</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>JUN SEO JANG</creatorcontrib><creatorcontrib>JAE HYEONG HONG</creatorcontrib><creatorcontrib>JIN HA HWANG</creatorcontrib><creatorcontrib>SOON SUNG AN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JUN SEO JANG</au><au>JAE HYEONG HONG</au><au>JIN HA HWANG</au><au>SOON SUNG AN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BUFFER CIRCUIT CAPABLE OF REDUCING NOISE</title><date>2023-01-02</date><risdate>2023</risdate><abstract>A buffer circuit may comprise: a power control circuit; an inverting circuit; and a voltage adjustment circuit. The power control circuit provides a voltage based on an input signal and a mode signal, and the inverting circuit may generate an output signal by input-receiving and inverting the voltage. The voltage adjustment circuit may adjust a voltage level based on the mode signal and the output signal. Therefore, the present invention is capable of improving a performance.
버퍼 회로는, 전원 제어 회로 및 인버팅 회로, 전압 조절 회로를 포함할 수 있다. 상기 전원 제어 회로는 입력 신호 및 모드 신호에 기초하여 전압을 제공하고, 상기 인버팅 회로는 전압을 입력 받아 반전하여 출력 신호를 생성할 수 있다. 상기 전압 조절 회로는 모드 신호 및 출력 신호에 기초하여 전압 레벨을 조절할 수 있다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | BUFFER CIRCUIT CAPABLE OF REDUCING NOISE |
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