PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING

Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed l...

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Hauptverfasser: AYGUEN KEMAL, SRINIVASAN SRIRAM, JIANG ZHENGUO, HARIRI HAIFA, ZHANG ZHICHAO
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creator AYGUEN KEMAL
SRINIVASAN SRIRAM
JIANG ZHENGUO
HARIRI HAIFA
ZHANG ZHICHAO
description Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect having a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end. According to present invention, miniaturization of form factor and increased levels of integration can be achieved for high performance. 본 명세서에 개시되는 실시예들은 전자 패키징된 어셈블리들을 포함한다. 실시예에서, 전자 패키지는 제1 및 제2 표면들을 포함한다. 제2 표면은 랜드 패드 개구에서의 랜드 패드를 갖는다. 랜드 패드는 외부 갭에 의해 랜드 패드 개구로부터 이격된다. 랜드 패드는 폐쇄 루프이다. 실시예에서, 전자 패키지는 소켓에 전기적으로 연결된다. 소켓은 제1 커넥터 및 제2 커넥터가 있는 인터커넥트를 갖는다. 인터커넥트의 제1 커넥터는 폐쇄 루프의 적어도 하나의 부분에 직접 연결된다. 실시예에서, 제1 커넥터가 폐쇄 루프의 적어도 2개 이상의 부분들에 연결될 때, 이러한 부분들은 내부 또는 외부 갭의 부분에 의해 서로 이격된다. 폐쇄 루프는 제1 단부로부터 제2 단부까지 연속적으로 연장되는 전도성 라인을 포함한다.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20210119274A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20210119274A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20210119274A3</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAsDqL-w4FzoYmCdDwu1yQ0JCHJXorESbRQ_x8XP8DpLW8vKCFNaBg8Bg0JNbgA5GNh3fkYE9SMxDDGDNYZCyUxa9BYEYozAb0L5ih2j-W5tdPPgziPXMl2bX3PbVuXe3u1zzxl1SvZSzmo2xUv_60vZuMrdQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING</title><source>esp@cenet</source><creator>AYGUEN KEMAL ; SRINIVASAN SRIRAM ; JIANG ZHENGUO ; HARIRI HAIFA ; ZHANG ZHICHAO</creator><creatorcontrib>AYGUEN KEMAL ; SRINIVASAN SRIRAM ; JIANG ZHENGUO ; HARIRI HAIFA ; ZHANG ZHICHAO</creatorcontrib><description>Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect having a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end. According to present invention, miniaturization of form factor and increased levels of integration can be achieved for high performance. 본 명세서에 개시되는 실시예들은 전자 패키징된 어셈블리들을 포함한다. 실시예에서, 전자 패키지는 제1 및 제2 표면들을 포함한다. 제2 표면은 랜드 패드 개구에서의 랜드 패드를 갖는다. 랜드 패드는 외부 갭에 의해 랜드 패드 개구로부터 이격된다. 랜드 패드는 폐쇄 루프이다. 실시예에서, 전자 패키지는 소켓에 전기적으로 연결된다. 소켓은 제1 커넥터 및 제2 커넥터가 있는 인터커넥트를 갖는다. 인터커넥트의 제1 커넥터는 폐쇄 루프의 적어도 하나의 부분에 직접 연결된다. 실시예에서, 제1 커넥터가 폐쇄 루프의 적어도 2개 이상의 부분들에 연결될 때, 이러한 부분들은 내부 또는 외부 갭의 부분에 의해 서로 이격된다. 폐쇄 루프는 제1 단부로부터 제2 단부까지 연속적으로 연장되는 전도성 라인을 포함한다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211005&amp;DB=EPODOC&amp;CC=KR&amp;NR=20210119274A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211005&amp;DB=EPODOC&amp;CC=KR&amp;NR=20210119274A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AYGUEN KEMAL</creatorcontrib><creatorcontrib>SRINIVASAN SRIRAM</creatorcontrib><creatorcontrib>JIANG ZHENGUO</creatorcontrib><creatorcontrib>HARIRI HAIFA</creatorcontrib><creatorcontrib>ZHANG ZHICHAO</creatorcontrib><title>PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING</title><description>Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect having a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end. According to present invention, miniaturization of form factor and increased levels of integration can be achieved for high performance. 본 명세서에 개시되는 실시예들은 전자 패키징된 어셈블리들을 포함한다. 실시예에서, 전자 패키지는 제1 및 제2 표면들을 포함한다. 제2 표면은 랜드 패드 개구에서의 랜드 패드를 갖는다. 랜드 패드는 외부 갭에 의해 랜드 패드 개구로부터 이격된다. 랜드 패드는 폐쇄 루프이다. 실시예에서, 전자 패키지는 소켓에 전기적으로 연결된다. 소켓은 제1 커넥터 및 제2 커넥터가 있는 인터커넥트를 갖는다. 인터커넥트의 제1 커넥터는 폐쇄 루프의 적어도 하나의 부분에 직접 연결된다. 실시예에서, 제1 커넥터가 폐쇄 루프의 적어도 2개 이상의 부분들에 연결될 때, 이러한 부분들은 내부 또는 외부 갭의 부분에 의해 서로 이격된다. 폐쇄 루프는 제1 단부로부터 제2 단부까지 연속적으로 연장되는 전도성 라인을 포함한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-w4FzoYmCdDwu1yQ0JCHJXorESbRQ_x8XP8DpLW8vKCFNaBg8Bg0JNbgA5GNh3fkYE9SMxDDGDNYZCyUxa9BYEYozAb0L5ih2j-W5tdPPgziPXMl2bX3PbVuXe3u1zzxl1SvZSzmo2xUv_60vZuMrdQ</recordid><startdate>20211005</startdate><enddate>20211005</enddate><creator>AYGUEN KEMAL</creator><creator>SRINIVASAN SRIRAM</creator><creator>JIANG ZHENGUO</creator><creator>HARIRI HAIFA</creator><creator>ZHANG ZHICHAO</creator><scope>EVB</scope></search><sort><creationdate>20211005</creationdate><title>PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING</title><author>AYGUEN KEMAL ; SRINIVASAN SRIRAM ; JIANG ZHENGUO ; HARIRI HAIFA ; ZHANG ZHICHAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20210119274A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AYGUEN KEMAL</creatorcontrib><creatorcontrib>SRINIVASAN SRIRAM</creatorcontrib><creatorcontrib>JIANG ZHENGUO</creatorcontrib><creatorcontrib>HARIRI HAIFA</creatorcontrib><creatorcontrib>ZHANG ZHICHAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AYGUEN KEMAL</au><au>SRINIVASAN SRIRAM</au><au>JIANG ZHENGUO</au><au>HARIRI HAIFA</au><au>ZHANG ZHICHAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING</title><date>2021-10-05</date><risdate>2021</risdate><abstract>Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect having a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end. According to present invention, miniaturization of form factor and increased levels of integration can be achieved for high performance. 본 명세서에 개시되는 실시예들은 전자 패키징된 어셈블리들을 포함한다. 실시예에서, 전자 패키지는 제1 및 제2 표면들을 포함한다. 제2 표면은 랜드 패드 개구에서의 랜드 패드를 갖는다. 랜드 패드는 외부 갭에 의해 랜드 패드 개구로부터 이격된다. 랜드 패드는 폐쇄 루프이다. 실시예에서, 전자 패키지는 소켓에 전기적으로 연결된다. 소켓은 제1 커넥터 및 제2 커넥터가 있는 인터커넥트를 갖는다. 인터커넥트의 제1 커넥터는 폐쇄 루프의 적어도 하나의 부분에 직접 연결된다. 실시예에서, 제1 커넥터가 폐쇄 루프의 적어도 2개 이상의 부분들에 연결될 때, 이러한 부분들은 내부 또는 외부 갭의 부분에 의해 서로 이격된다. 폐쇄 루프는 제1 단부로부터 제2 단부까지 연속적으로 연장되는 전도성 라인을 포함한다.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T18%3A52%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AYGUEN%20KEMAL&rft.date=2021-10-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20210119274A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true