Storage device and storage system including the same
A storage device and a storage system including the same are disclosed. The storage device according to the technical idea of the present disclosure includes: a reference clock pin configured to receive a reference clock from a host; a reference clock frequency discriminator configured to determine...
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| creator | JANG HYUN KYU NAM DONG WOO SHIN MYUNG SUB SEO SUNG HO JEONG YONG WOO NOH KWAN WOO |
| description | A storage device and a storage system including the same are disclosed. The storage device according to the technical idea of the present disclosure includes: a reference clock pin configured to receive a reference clock from a host; a reference clock frequency discriminator configured to determine a reference clock frequency from a reference clock received via the reference clock pin; and a device controller configured to perform link startup in a high-speed mode between the host and the storage device according to the determined reference clock frequency.
스토리지 장치 및 이를 포함하는 스토리지 시스템이 개시된다. 본 개시의 기술적 사상에 따른 스토리지 장치는, 호스트로부터 기준 클럭을 수신하도록 구성된 기준 클럭 핀, 기준 클럭 핀을 통해 수신한 기준 클럭으로부터 기준 클럭 주파수를 판별하도록 구성된 기준 클럭 주파수 판별기, 및 판별된 기준 클럭 주파수에 따라 호스트와 스토리지 장치 사이에서 고속 모드로 링크 스타트업을 수행하도록 구성된 장치 컨트롤러를 포함한다. |
| format | Patent |
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스토리지 장치 및 이를 포함하는 스토리지 시스템이 개시된다. 본 개시의 기술적 사상에 따른 스토리지 장치는, 호스트로부터 기준 클럭을 수신하도록 구성된 기준 클럭 핀, 기준 클럭 핀을 통해 수신한 기준 클럭으로부터 기준 클럭 주파수를 판별하도록 구성된 기준 클럭 주파수 판별기, 및 판별된 기준 클럭 주파수에 따라 호스트와 스토리지 장치 사이에서 고속 모드로 링크 스타트업을 수행하도록 구성된 장치 컨트롤러를 포함한다.</description><language>eng ; kor</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210830&DB=EPODOC&CC=KR&NR=20210106319A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210830&DB=EPODOC&CC=KR&NR=20210106319A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JANG HYUN KYU</creatorcontrib><creatorcontrib>NAM DONG WOO</creatorcontrib><creatorcontrib>SHIN MYUNG SUB</creatorcontrib><creatorcontrib>SEO SUNG HO</creatorcontrib><creatorcontrib>JEONG YONG WOO</creatorcontrib><creatorcontrib>NOH KWAN WOO</creatorcontrib><title>Storage device and storage system including the same</title><description>A storage device and a storage system including the same are disclosed. The storage device according to the technical idea of the present disclosure includes: a reference clock pin configured to receive a reference clock from a host; a reference clock frequency discriminator configured to determine a reference clock frequency from a reference clock received via the reference clock pin; and a device controller configured to perform link startup in a high-speed mode between the host and the storage device according to the determined reference clock frequency.
스토리지 장치 및 이를 포함하는 스토리지 시스템이 개시된다. 본 개시의 기술적 사상에 따른 스토리지 장치는, 호스트로부터 기준 클럭을 수신하도록 구성된 기준 클럭 핀, 기준 클럭 핀을 통해 수신한 기준 클럭으로부터 기준 클럭 주파수를 판별하도록 구성된 기준 클럭 주파수 판별기, 및 판별된 기준 클럭 주파수에 따라 호스트와 스토리지 장치 사이에서 고속 모드로 링크 스타트업을 수행하도록 구성된 장치 컨트롤러를 포함한다.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAJLskvSkxPVUhJLctMTlVIzEtRKIYKFVcWl6TmKmTmJeeUpmTmpSuUZAAFE3NTeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJvHeQkYGRoYGhgZmxoaWjMXGqANe3LX8</recordid><startdate>20210830</startdate><enddate>20210830</enddate><creator>JANG HYUN KYU</creator><creator>NAM DONG WOO</creator><creator>SHIN MYUNG SUB</creator><creator>SEO SUNG HO</creator><creator>JEONG YONG WOO</creator><creator>NOH KWAN WOO</creator><scope>EVB</scope></search><sort><creationdate>20210830</creationdate><title>Storage device and storage system including the same</title><author>JANG HYUN KYU ; NAM DONG WOO ; SHIN MYUNG SUB ; SEO SUNG HO ; JEONG YONG WOO ; NOH KWAN WOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20210106319A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>JANG HYUN KYU</creatorcontrib><creatorcontrib>NAM DONG WOO</creatorcontrib><creatorcontrib>SHIN MYUNG SUB</creatorcontrib><creatorcontrib>SEO SUNG HO</creatorcontrib><creatorcontrib>JEONG YONG WOO</creatorcontrib><creatorcontrib>NOH KWAN WOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JANG HYUN KYU</au><au>NAM DONG WOO</au><au>SHIN MYUNG SUB</au><au>SEO SUNG HO</au><au>JEONG YONG WOO</au><au>NOH KWAN WOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Storage device and storage system including the same</title><date>2021-08-30</date><risdate>2021</risdate><abstract>A storage device and a storage system including the same are disclosed. The storage device according to the technical idea of the present disclosure includes: a reference clock pin configured to receive a reference clock from a host; a reference clock frequency discriminator configured to determine a reference clock frequency from a reference clock received via the reference clock pin; and a device controller configured to perform link startup in a high-speed mode between the host and the storage device according to the determined reference clock frequency.
스토리지 장치 및 이를 포함하는 스토리지 시스템이 개시된다. 본 개시의 기술적 사상에 따른 스토리지 장치는, 호스트로부터 기준 클럭을 수신하도록 구성된 기준 클럭 핀, 기준 클럭 핀을 통해 수신한 기준 클럭으로부터 기준 클럭 주파수를 판별하도록 구성된 기준 클럭 주파수 판별기, 및 판별된 기준 클럭 주파수에 따라 호스트와 스토리지 장치 사이에서 고속 모드로 링크 스타트업을 수행하도록 구성된 장치 컨트롤러를 포함한다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Storage device and storage system including the same |
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