METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES
A manufacturing method of a semiconductor package encapsulates a plurality of semiconductor chips in a carrier and exposes one surface of the semiconductor chips, on which chip pads are formed, from the first surface of the carrier. An alignment error of each of the semiconductor chips with respect...
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| creator | JOO CHANG EUN CHOI GYU JIN |
| description | A manufacturing method of a semiconductor package encapsulates a plurality of semiconductor chips in a carrier and exposes one surface of the semiconductor chips, on which chip pads are formed, from the first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. In order to correct the alignment error, a redistribution line structure having redistribution lines electrically connected to the chip pads is formed on the first surface of the carrier by reflecting scattered correction values for each layer. External connection terminals electrically connected to the outermost redistribution lines are formed on the redistribution line structure.
반도체 패키지의 제조 방법에 있어서, 캐리어에 복수 개의 반도체 칩들을 캡슐화하되, 칩 패드들이 형성된 상기 반도체 칩의 일면이 상기 캐리어의 제1 면으로부터 노출되도록 한다. 상기 캐리어에 대한 상기 반도체 칩들 각각의 정렬 오차를 측정한다. 상기 정렬 오차를 보정하기 위하여 분산된 층별 보정값들을 반영하여 상기 캐리어의 제1 면 상에 상기 칩 패드들과 전기적으로 연결되는 재배선들을 갖는 재배선 구조물을 형성한다. 상기 재배선 구조물 상에 최외각 재배선들과 전기적으로 연결되는 외부 접속 단자들을 형성한다. |
| format | Patent |
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반도체 패키지의 제조 방법에 있어서, 캐리어에 복수 개의 반도체 칩들을 캡슐화하되, 칩 패드들이 형성된 상기 반도체 칩의 일면이 상기 캐리어의 제1 면으로부터 노출되도록 한다. 상기 캐리어에 대한 상기 반도체 칩들 각각의 정렬 오차를 측정한다. 상기 정렬 오차를 보정하기 위하여 분산된 층별 보정값들을 반영하여 상기 캐리어의 제1 면 상에 상기 칩 패드들과 전기적으로 연결되는 재배선들을 갖는 재배선 구조물을 형성한다. 상기 재배선 구조물 상에 최외각 재배선들과 전기적으로 연결되는 외부 접속 단자들을 형성한다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210623&DB=EPODOC&CC=KR&NR=20210075558A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210623&DB=EPODOC&CC=KR&NR=20210075558A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JOO CHANG EUN</creatorcontrib><creatorcontrib>CHOI GYU JIN</creatorcontrib><title>METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES</title><description>A manufacturing method of a semiconductor package encapsulates a plurality of semiconductor chips in a carrier and exposes one surface of the semiconductor chips, on which chip pads are formed, from the first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. In order to correct the alignment error, a redistribution line structure having redistribution lines electrically connected to the chip pads is formed on the first surface of the carrier by reflecting scattered correction values for each layer. External connection terminals electrically connected to the outermost redistribution lines are formed on the redistribution line structure.
반도체 패키지의 제조 방법에 있어서, 캐리어에 복수 개의 반도체 칩들을 캡슐화하되, 칩 패드들이 형성된 상기 반도체 칩의 일면이 상기 캐리어의 제1 면으로부터 노출되도록 한다. 상기 캐리어에 대한 상기 반도체 칩들 각각의 정렬 오차를 측정한다. 상기 정렬 오차를 보정하기 위하여 분산된 층별 보정값들을 반영하여 상기 캐리어의 제1 면 상에 상기 칩 패드들과 전기적으로 연결되는 재배선들을 갖는 재배선 구조물을 형성한다. 상기 재배선 구조물 상에 최외각 재배선들과 전기적으로 연결되는 외부 접속 단자들을 형성한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzdQ3x8HdR8HdT8HX0C3VzdA4JDfL0c1cIdvX1dPb3cwl1DvEPUghwdPZ2dHcN5mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgZGhgYG5qamphaOxsSpAgCGTia_</recordid><startdate>20210623</startdate><enddate>20210623</enddate><creator>JOO CHANG EUN</creator><creator>CHOI GYU JIN</creator><scope>EVB</scope></search><sort><creationdate>20210623</creationdate><title>METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES</title><author>JOO CHANG EUN ; CHOI GYU JIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20210075558A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JOO CHANG EUN</creatorcontrib><creatorcontrib>CHOI GYU JIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JOO CHANG EUN</au><au>CHOI GYU JIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES</title><date>2021-06-23</date><risdate>2021</risdate><abstract>A manufacturing method of a semiconductor package encapsulates a plurality of semiconductor chips in a carrier and exposes one surface of the semiconductor chips, on which chip pads are formed, from the first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. In order to correct the alignment error, a redistribution line structure having redistribution lines electrically connected to the chip pads is formed on the first surface of the carrier by reflecting scattered correction values for each layer. External connection terminals electrically connected to the outermost redistribution lines are formed on the redistribution line structure.
반도체 패키지의 제조 방법에 있어서, 캐리어에 복수 개의 반도체 칩들을 캡슐화하되, 칩 패드들이 형성된 상기 반도체 칩의 일면이 상기 캐리어의 제1 면으로부터 노출되도록 한다. 상기 캐리어에 대한 상기 반도체 칩들 각각의 정렬 오차를 측정한다. 상기 정렬 오차를 보정하기 위하여 분산된 층별 보정값들을 반영하여 상기 캐리어의 제1 면 상에 상기 칩 패드들과 전기적으로 연결되는 재배선들을 갖는 재배선 구조물을 형성한다. 상기 재배선 구조물 상에 최외각 재배선들과 전기적으로 연결되는 외부 접속 단자들을 형성한다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES |
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