SEMICONDUCTOR PACKAGES HAVING VIAS
Provided is a semiconductor package, which includes: a lower redistribution layer including an insulating pattern having an opening unit and a via filling the opening unit; a first semiconductor chip including a chip pad, a protection layer, and a pad bump connected to the chip pad; and a first enca...
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| creator | JOO CHANG EUN CHOI GYU JIN |
| description | Provided is a semiconductor package, which includes: a lower redistribution layer including an insulating pattern having an opening unit and a via filling the opening unit; a first semiconductor chip including a chip pad, a protection layer, and a pad bump connected to the chip pad; and a first encapsulant covering the lower redistribution layer and the first semiconductor chip. The opening unit opens a lower surface and a side surface of the pad bump, and the via is in contact with the lower surface and the side surface of the pad bump. The contact area of the via with the pad bump increases, so as to prevent and reduce delamination at the interface between the pad bump and the via.
반도체 패키지는 개구부를 갖는 절연 패턴 및 상기 개구부를 채우는 비아를 포함하는 하부 재배선층; 칩 패드, 보호층 및 칩 패드에 연결되는 패드 범프를 포함하는 제1 반도체 칩; 및 상기 하부 재배선층 및 상기 제1 반도체 칩을 덮는 제1 봉지재를 포함한다. 상기 개구부는 상기 패드 범프의 하면 및 측면을 오픈시키며, 상기 비아는 상기 패드 범프의 상기 하면 및 상기 측면과 접한다. |
| format | Patent |
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반도체 패키지는 개구부를 갖는 절연 패턴 및 상기 개구부를 채우는 비아를 포함하는 하부 재배선층; 칩 패드, 보호층 및 칩 패드에 연결되는 패드 범프를 포함하는 제1 반도체 칩; 및 상기 하부 재배선층 및 상기 제1 반도체 칩을 덮는 제1 봉지재를 포함한다. 상기 개구부는 상기 패드 범프의 하면 및 측면을 오픈시키며, 상기 비아는 상기 패드 범프의 상기 하면 및 상기 측면과 접한다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210520&DB=EPODOC&CC=KR&NR=20210056751A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210520&DB=EPODOC&CC=KR&NR=20210056751A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JOO CHANG EUN</creatorcontrib><creatorcontrib>CHOI GYU JIN</creatorcontrib><title>SEMICONDUCTOR PACKAGES HAVING VIAS</title><description>Provided is a semiconductor package, which includes: a lower redistribution layer including an insulating pattern having an opening unit and a via filling the opening unit; a first semiconductor chip including a chip pad, a protection layer, and a pad bump connected to the chip pad; and a first encapsulant covering the lower redistribution layer and the first semiconductor chip. The opening unit opens a lower surface and a side surface of the pad bump, and the via is in contact with the lower surface and the side surface of the pad bump. The contact area of the via with the pad bump increases, so as to prevent and reduce delamination at the interface between the pad bump and the via.
반도체 패키지는 개구부를 갖는 절연 패턴 및 상기 개구부를 채우는 비아를 포함하는 하부 재배선층; 칩 패드, 보호층 및 칩 패드에 연결되는 패드 범프를 포함하는 제1 반도체 칩; 및 상기 하부 재배선층 및 상기 제1 반도체 칩을 덮는 제1 봉지재를 포함한다. 상기 개구부는 상기 패드 범프의 하면 및 측면을 오픈시키며, 상기 비아는 상기 패드 범프의 상기 하면 및 상기 측면과 접한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAKdvX1dPb3cwl1DvEPUghwdPZ2dHcNVvBwDPP0c1cI83QM5mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgZGhgYGpmbmpoaOxsSpAgDFGSNN</recordid><startdate>20210520</startdate><enddate>20210520</enddate><creator>JOO CHANG EUN</creator><creator>CHOI GYU JIN</creator><scope>EVB</scope></search><sort><creationdate>20210520</creationdate><title>SEMICONDUCTOR PACKAGES HAVING VIAS</title><author>JOO CHANG EUN ; CHOI GYU JIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20210056751A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JOO CHANG EUN</creatorcontrib><creatorcontrib>CHOI GYU JIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JOO CHANG EUN</au><au>CHOI GYU JIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGES HAVING VIAS</title><date>2021-05-20</date><risdate>2021</risdate><abstract>Provided is a semiconductor package, which includes: a lower redistribution layer including an insulating pattern having an opening unit and a via filling the opening unit; a first semiconductor chip including a chip pad, a protection layer, and a pad bump connected to the chip pad; and a first encapsulant covering the lower redistribution layer and the first semiconductor chip. The opening unit opens a lower surface and a side surface of the pad bump, and the via is in contact with the lower surface and the side surface of the pad bump. The contact area of the via with the pad bump increases, so as to prevent and reduce delamination at the interface between the pad bump and the via.
반도체 패키지는 개구부를 갖는 절연 패턴 및 상기 개구부를 채우는 비아를 포함하는 하부 재배선층; 칩 패드, 보호층 및 칩 패드에 연결되는 패드 범프를 포함하는 제1 반도체 칩; 및 상기 하부 재배선층 및 상기 제1 반도체 칩을 덮는 제1 봉지재를 포함한다. 상기 개구부는 상기 패드 범프의 하면 및 측면을 오픈시키며, 상기 비아는 상기 패드 범프의 상기 하면 및 상기 측면과 접한다.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR PACKAGES HAVING VIAS |
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