FAN-OUT SEMICONDUCTOR PACKAGE
The present invention relates to a fan-out semiconductor package which comprises: a frame including one or more layers of wiring layers and having a through-hole; a semiconductor chip disposed in the through-hole and including an active surface with a connection pad disposed thereon and an inactive...
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| creator | CHOI WON KIM SUNG HOAN BAE SUNG HAWN KIM JUNG SOO |
| description | The present invention relates to a fan-out semiconductor package which comprises: a frame including one or more layers of wiring layers and having a through-hole; a semiconductor chip disposed in the through-hole and including an active surface with a connection pad disposed thereon and an inactive surface opposite to the active surface; an encapsulant covering at least a portion of each of the frame and the inactive surface of the semiconductor chip and having a first opening opening at least a portion of the wiring layer; an insulating layer disposed on the encapsulant and having a second opening formed in the first opening to open at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening and electrically connecting the wiring layer to the conductive pattern layer; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad. The present invention can increase the reliability of the conductive via.
본 개시는 한층 이상의 배선층을 포함하며, 관통홀을 갖는 프레임; 상기 관통홀에 배치되며, 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩; 상기 프레임 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며, 상기 배선층의 적어도 일부를 오픈시키는 제1개구부를 갖는 봉합재; 상기 봉합재 상에 배치되며, 상기 제1개구부 내에 형성되어 상기 배선층의 적어도 일부를 오픈시키는 제2개구부를 갖는 절연층; 상기 절연층 상에 배치된 도전성 패턴층; 상기 제2개구부에 배치되며, 상기 배선층 및 상기 도전성 패턴층을 전기적으로 연결하는 도전성 비아; 및 상기 프레임 및 상기 반도체칩의 활성면 상에 배치되며, 한층 이상의 재배선층을 포함하는 연결구조체; 를 포함하며, 상기 도전성 패턴층 및 상기 재배선층은 상기 접속패드와 전기적으로 연결된, 팬-아웃 반도체 패키지에 관한 것이다. |
| format | Patent |
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본 개시는 한층 이상의 배선층을 포함하며, 관통홀을 갖는 프레임; 상기 관통홀에 배치되며, 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩; 상기 프레임 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며, 상기 배선층의 적어도 일부를 오픈시키는 제1개구부를 갖는 봉합재; 상기 봉합재 상에 배치되며, 상기 제1개구부 내에 형성되어 상기 배선층의 적어도 일부를 오픈시키는 제2개구부를 갖는 절연층; 상기 절연층 상에 배치된 도전성 패턴층; 상기 제2개구부에 배치되며, 상기 배선층 및 상기 도전성 패턴층을 전기적으로 연결하는 도전성 비아; 및 상기 프레임 및 상기 반도체칩의 활성면 상에 배치되며, 한층 이상의 재배선층을 포함하는 연결구조체; 를 포함하며, 상기 도전성 패턴층 및 상기 재배선층은 상기 접속패드와 전기적으로 연결된, 팬-아웃 반도체 패키지에 관한 것이다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200217&DB=EPODOC&CC=KR&NR=20200016624A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200217&DB=EPODOC&CC=KR&NR=20200016624A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHOI WON</creatorcontrib><creatorcontrib>KIM SUNG HOAN</creatorcontrib><creatorcontrib>BAE SUNG HAWN</creatorcontrib><creatorcontrib>KIM JUNG SOO</creatorcontrib><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><description>The present invention relates to a fan-out semiconductor package which comprises: a frame including one or more layers of wiring layers and having a through-hole; a semiconductor chip disposed in the through-hole and including an active surface with a connection pad disposed thereon and an inactive surface opposite to the active surface; an encapsulant covering at least a portion of each of the frame and the inactive surface of the semiconductor chip and having a first opening opening at least a portion of the wiring layer; an insulating layer disposed on the encapsulant and having a second opening formed in the first opening to open at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening and electrically connecting the wiring layer to the conductive pattern layer; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad. The present invention can increase the reliability of the conductive via.
본 개시는 한층 이상의 배선층을 포함하며, 관통홀을 갖는 프레임; 상기 관통홀에 배치되며, 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩; 상기 프레임 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며, 상기 배선층의 적어도 일부를 오픈시키는 제1개구부를 갖는 봉합재; 상기 봉합재 상에 배치되며, 상기 제1개구부 내에 형성되어 상기 배선층의 적어도 일부를 오픈시키는 제2개구부를 갖는 절연층; 상기 절연층 상에 배치된 도전성 패턴층; 상기 제2개구부에 배치되며, 상기 배선층 및 상기 도전성 패턴층을 전기적으로 연결하는 도전성 비아; 및 상기 프레임 및 상기 반도체칩의 활성면 상에 배치되며, 한층 이상의 재배선층을 포함하는 연결구조체; 를 포함하며, 상기 도전성 패턴층 및 상기 재배선층은 상기 접속패드와 전기적으로 연결된, 팬-아웃 반도체 패키지에 관한 것이다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB1c_TT9Q8NUQh29fV09vdzCXUO8Q9SCHB09nZ0d-VhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGRgYGBoZmZkYmjsbEqQIAD6Yh0w</recordid><startdate>20200217</startdate><enddate>20200217</enddate><creator>CHOI WON</creator><creator>KIM SUNG HOAN</creator><creator>BAE SUNG HAWN</creator><creator>KIM JUNG SOO</creator><scope>EVB</scope></search><sort><creationdate>20200217</creationdate><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><author>CHOI WON ; KIM SUNG HOAN ; BAE SUNG HAWN ; KIM JUNG SOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20200016624A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHOI WON</creatorcontrib><creatorcontrib>KIM SUNG HOAN</creatorcontrib><creatorcontrib>BAE SUNG HAWN</creatorcontrib><creatorcontrib>KIM JUNG SOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHOI WON</au><au>KIM SUNG HOAN</au><au>BAE SUNG HAWN</au><au>KIM JUNG SOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FAN-OUT SEMICONDUCTOR PACKAGE</title><date>2020-02-17</date><risdate>2020</risdate><abstract>The present invention relates to a fan-out semiconductor package which comprises: a frame including one or more layers of wiring layers and having a through-hole; a semiconductor chip disposed in the through-hole and including an active surface with a connection pad disposed thereon and an inactive surface opposite to the active surface; an encapsulant covering at least a portion of each of the frame and the inactive surface of the semiconductor chip and having a first opening opening at least a portion of the wiring layer; an insulating layer disposed on the encapsulant and having a second opening formed in the first opening to open at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening and electrically connecting the wiring layer to the conductive pattern layer; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad. The present invention can increase the reliability of the conductive via.
본 개시는 한층 이상의 배선층을 포함하며, 관통홀을 갖는 프레임; 상기 관통홀에 배치되며, 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩; 상기 프레임 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며, 상기 배선층의 적어도 일부를 오픈시키는 제1개구부를 갖는 봉합재; 상기 봉합재 상에 배치되며, 상기 제1개구부 내에 형성되어 상기 배선층의 적어도 일부를 오픈시키는 제2개구부를 갖는 절연층; 상기 절연층 상에 배치된 도전성 패턴층; 상기 제2개구부에 배치되며, 상기 배선층 및 상기 도전성 패턴층을 전기적으로 연결하는 도전성 비아; 및 상기 프레임 및 상기 반도체칩의 활성면 상에 배치되며, 한층 이상의 재배선층을 포함하는 연결구조체; 를 포함하며, 상기 도전성 패턴층 및 상기 재배선층은 상기 접속패드와 전기적으로 연결된, 팬-아웃 반도체 패키지에 관한 것이다.</abstract><oa>free_for_read</oa></addata></record> |
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| title | FAN-OUT SEMICONDUCTOR PACKAGE |
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