ELECTRONIC COMPONENT PACKAGE

The present disclosure relates to an electronic component package. The electronic component package comprises a core member including an insulating layer and having a first through hole penetrating the insulating layer, a semiconductor chip disposed in the first through hole and having an active sur...

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Hauptverfasser: KUROYANAGI AKIHISA, MYUNG JUN WOO, LEE JAE KUL
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Sprache:eng ; kor
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creator KUROYANAGI AKIHISA
MYUNG JUN WOO
LEE JAE KUL
description The present disclosure relates to an electronic component package. The electronic component package comprises a core member including an insulating layer and having a first through hole penetrating the insulating layer, a semiconductor chip disposed in the first through hole and having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of each of the core member and the inactive surface of the semiconductor chip and filling at least a portion of the first through hole; a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad; a backside metal layer disposed on the encapsulant and covering at least the inactive surface of the semiconductor chip; and a backside metal via penetrating the encapsulant and connecting one surface of the backside metal layer and the insulating layer. The backside metal via is in contact with one surface of the insulating layer. It is possible to effectively shield electromagnetic waves. 본 개시는 절연층을 포함하며 상기 절연층을 관통하는 제1관통홀을 갖는 코어부재, 상기 제1관통홀에 배치되며 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩, 상기 코어부재 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며 상기 제1관통홀의 적어도 일부를 채우는 봉합재, 상기 코어부재 및 상기 반도체칩의 활성면 상에 배치되며 상기 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결부재, 상기 봉합재 상에 배치되며 상기 반도체칩의 비활성면을 적어도 커버하는 백사이드 금속층, 및 상기 봉합재를 관통하며 상기 백사이드 금속층 및 상기 절연층의 일면을 연결하는 백사이드 금속비아를 포함하며, 상기 백사이드 금속비아는 상기 절연층의 일면과 접하는 전자부품 패키지에 관한 것이다.
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The electronic component package comprises a core member including an insulating layer and having a first through hole penetrating the insulating layer, a semiconductor chip disposed in the first through hole and having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of each of the core member and the inactive surface of the semiconductor chip and filling at least a portion of the first through hole; a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad; a backside metal layer disposed on the encapsulant and covering at least the inactive surface of the semiconductor chip; and a backside metal via penetrating the encapsulant and connecting one surface of the backside metal layer and the insulating layer. The backside metal via is in contact with one surface of the insulating layer. It is possible to effectively shield electromagnetic waves. 본 개시는 절연층을 포함하며 상기 절연층을 관통하는 제1관통홀을 갖는 코어부재, 상기 제1관통홀에 배치되며 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩, 상기 코어부재 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며 상기 제1관통홀의 적어도 일부를 채우는 봉합재, 상기 코어부재 및 상기 반도체칩의 활성면 상에 배치되며 상기 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결부재, 상기 봉합재 상에 배치되며 상기 반도체칩의 비활성면을 적어도 커버하는 백사이드 금속층, 및 상기 봉합재를 관통하며 상기 백사이드 금속층 및 상기 절연층의 일면을 연결하는 백사이드 금속비아를 포함하며, 상기 백사이드 금속비아는 상기 절연층의 일면과 접하는 전자부품 패키지에 관한 것이다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191212&amp;DB=EPODOC&amp;CC=KR&amp;NR=20190138108A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191212&amp;DB=EPODOC&amp;CC=KR&amp;NR=20190138108A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUROYANAGI AKIHISA</creatorcontrib><creatorcontrib>MYUNG JUN WOO</creatorcontrib><creatorcontrib>LEE JAE KUL</creatorcontrib><title>ELECTRONIC COMPONENT PACKAGE</title><description>The present disclosure relates to an electronic component package. The electronic component package comprises a core member including an insulating layer and having a first through hole penetrating the insulating layer, a semiconductor chip disposed in the first through hole and having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of each of the core member and the inactive surface of the semiconductor chip and filling at least a portion of the first through hole; a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad; a backside metal layer disposed on the encapsulant and covering at least the inactive surface of the semiconductor chip; and a backside metal via penetrating the encapsulant and connecting one surface of the backside metal layer and the insulating layer. The backside metal via is in contact with one surface of the insulating layer. It is possible to effectively shield electromagnetic waves. 본 개시는 절연층을 포함하며 상기 절연층을 관통하는 제1관통홀을 갖는 코어부재, 상기 제1관통홀에 배치되며 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩, 상기 코어부재 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며 상기 제1관통홀의 적어도 일부를 채우는 봉합재, 상기 코어부재 및 상기 반도체칩의 활성면 상에 배치되며 상기 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결부재, 상기 봉합재 상에 배치되며 상기 반도체칩의 비활성면을 적어도 커버하는 백사이드 금속층, 및 상기 봉합재를 관통하며 상기 백사이드 금속층 및 상기 절연층의 일면을 연결하는 백사이드 금속비아를 포함하며, 상기 백사이드 금속비아는 상기 절연층의 일면과 접하는 전자부품 패키지에 관한 것이다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJBx9XF1Dgny9_N0VnD29w3w93P1C1EIcHT2dnR35WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgaGlgaGxhaGBhaOxsSpAgD0sCGo</recordid><startdate>20191212</startdate><enddate>20191212</enddate><creator>KUROYANAGI AKIHISA</creator><creator>MYUNG JUN WOO</creator><creator>LEE JAE KUL</creator><scope>EVB</scope></search><sort><creationdate>20191212</creationdate><title>ELECTRONIC COMPONENT PACKAGE</title><author>KUROYANAGI AKIHISA ; MYUNG JUN WOO ; LEE JAE KUL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190138108A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KUROYANAGI AKIHISA</creatorcontrib><creatorcontrib>MYUNG JUN WOO</creatorcontrib><creatorcontrib>LEE JAE KUL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUROYANAGI AKIHISA</au><au>MYUNG JUN WOO</au><au>LEE JAE KUL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ELECTRONIC COMPONENT PACKAGE</title><date>2019-12-12</date><risdate>2019</risdate><abstract>The present disclosure relates to an electronic component package. The electronic component package comprises a core member including an insulating layer and having a first through hole penetrating the insulating layer, a semiconductor chip disposed in the first through hole and having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of each of the core member and the inactive surface of the semiconductor chip and filling at least a portion of the first through hole; a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad; a backside metal layer disposed on the encapsulant and covering at least the inactive surface of the semiconductor chip; and a backside metal via penetrating the encapsulant and connecting one surface of the backside metal layer and the insulating layer. The backside metal via is in contact with one surface of the insulating layer. It is possible to effectively shield electromagnetic waves. 본 개시는 절연층을 포함하며 상기 절연층을 관통하는 제1관통홀을 갖는 코어부재, 상기 제1관통홀에 배치되며 접속패드가 배치된 활성면 및 상기 활성면의 반대측인 비활성면을 갖는 반도체칩, 상기 코어부재 및 상기 반도체칩의 비활성면 각각의 적어도 일부를 덮으며 상기 제1관통홀의 적어도 일부를 채우는 봉합재, 상기 코어부재 및 상기 반도체칩의 활성면 상에 배치되며 상기 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결부재, 상기 봉합재 상에 배치되며 상기 반도체칩의 비활성면을 적어도 커버하는 백사이드 금속층, 및 상기 봉합재를 관통하며 상기 백사이드 금속층 및 상기 절연층의 일면을 연결하는 백사이드 금속비아를 포함하며, 상기 백사이드 금속비아는 상기 절연층의 일면과 접하는 전자부품 패키지에 관한 것이다.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title ELECTRONIC COMPONENT PACKAGE
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