SRAM CELL FOR GENERATING TRUE RANDOM NUMBER AND SRAM CELL ARRY DRIVING CIRCUIT USING THE SAME
The present invention relates to a technique capable of the generation a true random number of a natural state by using static noise margin characteristics and read noise margin characteristics of a static random access memory (SRAM). A first aspect of the present invention is to reduce a noise marg...
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description | The present invention relates to a technique capable of the generation a true random number of a natural state by using static noise margin characteristics and read noise margin characteristics of a static random access memory (SRAM). A first aspect of the present invention is to reduce a noise margin by forming first and second NMOS transistors constituting a latch to be smaller than or equal to a size of each of first and second access NMOS transistors. A second aspect of the present invention is to reduce the noise margin by setting a voltage between a first node of a first inverter and a second node of a second inverter constituting the latch to an intermediate level between an internal power supply voltage and a ground voltage.
본 발명은 에스램(SRAM)의 스태틱 노이즈 마진(Static Noise Margin) 특성과 리드 노이즈 마진(Read Noise Margin) 특성을 이용하여 자연상태의 진난수를 발생할 수 있도록 한 기술에 관한 것이다. 본 발명은 래치를 구성하는 제1,2엔모스 트랜지스터 각각의 사이즈를 제1,2억세스용 엔모스 트랜지스터 각각의 사이즈보다 작거나 같게 형성하여 노이즈 마진을 줄인 것을 제1특징으로 한다. 본 발명은 래치를 구성하는 제1인버터의 제1노드와 제2인버터의 제2노드의 전압을 내부전원전압과 그라운드 전압의 중간 레벨로 설정하여 노이즈 마진을 줄인 것을 제2특징으로 한다. |
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본 발명은 에스램(SRAM)의 스태틱 노이즈 마진(Static Noise Margin) 특성과 리드 노이즈 마진(Read Noise Margin) 특성을 이용하여 자연상태의 진난수를 발생할 수 있도록 한 기술에 관한 것이다. 본 발명은 래치를 구성하는 제1,2엔모스 트랜지스터 각각의 사이즈를 제1,2억세스용 엔모스 트랜지스터 각각의 사이즈보다 작거나 같게 형성하여 노이즈 마진을 줄인 것을 제1특징으로 한다. 본 발명은 래치를 구성하는 제1인버터의 제1노드와 제2인버터의 제2노드의 전압을 내부전원전압과 그라운드 전압의 중간 레벨로 설정하여 노이즈 마진을 줄인 것을 제2특징으로 한다.</description><language>eng ; kor</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190812&DB=EPODOC&CC=KR&NR=20190093905A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190812&DB=EPODOC&CC=KR&NR=20190093905A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AHN, SANG WOOK</creatorcontrib><title>SRAM CELL FOR GENERATING TRUE RANDOM NUMBER AND SRAM CELL ARRY DRIVING CIRCUIT USING THE SAME</title><description>The present invention relates to a technique capable of the generation a true random number of a natural state by using static noise margin characteristics and read noise margin characteristics of a static random access memory (SRAM). A first aspect of the present invention is to reduce a noise margin by forming first and second NMOS transistors constituting a latch to be smaller than or equal to a size of each of first and second access NMOS transistors. A second aspect of the present invention is to reduce the noise margin by setting a voltage between a first node of a first inverter and a second node of a second inverter constituting the latch to an intermediate level between an internal power supply voltage and a ground voltage.
본 발명은 에스램(SRAM)의 스태틱 노이즈 마진(Static Noise Margin) 특성과 리드 노이즈 마진(Read Noise Margin) 특성을 이용하여 자연상태의 진난수를 발생할 수 있도록 한 기술에 관한 것이다. 본 발명은 래치를 구성하는 제1,2엔모스 트랜지스터 각각의 사이즈를 제1,2억세스용 엔모스 트랜지스터 각각의 사이즈보다 작거나 같게 형성하여 노이즈 마진을 줄인 것을 제1특징으로 한다. 본 발명은 래치를 구성하는 제1인버터의 제1노드와 제2인버터의 제2노드의 전압을 내부전원전압과 그라운드 전압의 중간 레벨로 설정하여 노이즈 마진을 줄인 것을 제2특징으로 한다.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIgNDnL0VXB29fFRcPMPUnB39XMNcgzx9HNXCAkKdVUIcvRz8fdV8Av1dXINUgByFBDqHYOCIhVcgjzDQKqdPYOcQz1DFEKDwXo9XBWCHX1deRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJvHeQkYGhpYGBpbGlgamjMXGqAHFsMws</recordid><startdate>20190812</startdate><enddate>20190812</enddate><creator>AHN, SANG WOOK</creator><scope>EVB</scope></search><sort><creationdate>20190812</creationdate><title>SRAM CELL FOR GENERATING TRUE RANDOM NUMBER AND SRAM CELL ARRY DRIVING CIRCUIT USING THE SAME</title><author>AHN, SANG WOOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190093905A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2019</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>AHN, SANG WOOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AHN, SANG WOOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SRAM CELL FOR GENERATING TRUE RANDOM NUMBER AND SRAM CELL ARRY DRIVING CIRCUIT USING THE SAME</title><date>2019-08-12</date><risdate>2019</risdate><abstract>The present invention relates to a technique capable of the generation a true random number of a natural state by using static noise margin characteristics and read noise margin characteristics of a static random access memory (SRAM). A first aspect of the present invention is to reduce a noise margin by forming first and second NMOS transistors constituting a latch to be smaller than or equal to a size of each of first and second access NMOS transistors. A second aspect of the present invention is to reduce the noise margin by setting a voltage between a first node of a first inverter and a second node of a second inverter constituting the latch to an intermediate level between an internal power supply voltage and a ground voltage.
본 발명은 에스램(SRAM)의 스태틱 노이즈 마진(Static Noise Margin) 특성과 리드 노이즈 마진(Read Noise Margin) 특성을 이용하여 자연상태의 진난수를 발생할 수 있도록 한 기술에 관한 것이다. 본 발명은 래치를 구성하는 제1,2엔모스 트랜지스터 각각의 사이즈를 제1,2억세스용 엔모스 트랜지스터 각각의 사이즈보다 작거나 같게 형성하여 노이즈 마진을 줄인 것을 제1특징으로 한다. 본 발명은 래치를 구성하는 제1인버터의 제1노드와 제2인버터의 제2노드의 전압을 내부전원전압과 그라운드 전압의 중간 레벨로 설정하여 노이즈 마진을 줄인 것을 제2특징으로 한다.</abstract><oa>free_for_read</oa></addata></record> |
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title | SRAM CELL FOR GENERATING TRUE RANDOM NUMBER AND SRAM CELL ARRY DRIVING CIRCUIT USING THE SAME |
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