이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들
이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들의 실시예들이 설명된다. 일부 실시예들에서, 하드웨어 이종 스케줄러는 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 상에서의 실행을 위해 명령어들을 디스패치하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소에 의해 처리될 코드 조각에 대응하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 중의 적어도 하나의 이종 처리 요소에 대한 고유 명령어들이다. The present disclosure provides a processor...
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| creator | MARR DEBORAH T VAN DOREN STEPHEN R SHEFFIELD DAVID B SANKARAN RAJESH M MCDONNELL NIALL D VENKATESH GANESH O'HANLON MICHAEL A CORBAL JESUS YAMADA KOICHI NURVITADHI ERIKO VALENTINE ROBERT MANLEY DWIGHT P BRADFORD DENNIS R GLOSSOP KENT D CARTER NICHOLAS P NEIGER GILBERT COOK JEFFREY J MOSUR LOKPRAVEEN B MISHRA ASIT K RANGANATHAN NARAYAN CHARNEY MARK J GROCHOWSKI EDWARD T GRECO RICHARD J NUZMAN JOSEPH PEARCE JONATHAN D FLETCHER THOMAS D CAPRIOLI PAUL DRYSDALE TRACY GARRETT |
| description | 이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들의 실시예들이 설명된다. 일부 실시예들에서, 하드웨어 이종 스케줄러는 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 상에서의 실행을 위해 명령어들을 디스패치하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소에 의해 처리될 코드 조각에 대응하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 중의 적어도 하나의 이종 처리 요소에 대한 고유 명령어들이다.
The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20190093568A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20190093568A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20190093568A3</originalsourceid><addsrcrecordid>eNrjZHB8M3fLm0WtCm92b3k7ecXbntY3c1sU3sxpeTt1jsKb7jlvupa8bZ3zevISHYXXG1a-3jQVyuxXeDNv6ZudM4BcHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oS7x1kZGBoaWBgaWxqZuFoTJwqAFE3Q-c</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들</title><source>esp@cenet</source><creator>MARR DEBORAH T ; VAN DOREN STEPHEN R ; SHEFFIELD DAVID B ; SANKARAN RAJESH M ; MCDONNELL NIALL D ; VENKATESH GANESH ; O'HANLON MICHAEL A ; CORBAL JESUS ; YAMADA KOICHI ; NURVITADHI ERIKO ; VALENTINE ROBERT ; MANLEY DWIGHT P ; BRADFORD DENNIS R ; GLOSSOP KENT D ; CARTER NICHOLAS P ; NEIGER GILBERT ; COOK JEFFREY J ; MOSUR LOKPRAVEEN B ; MISHRA ASIT K ; RANGANATHAN NARAYAN ; CHARNEY MARK J ; GROCHOWSKI EDWARD T ; GRECO RICHARD J ; NUZMAN JOSEPH ; PEARCE JONATHAN D ; FLETCHER THOMAS D ; CAPRIOLI PAUL ; DRYSDALE TRACY GARRETT</creator><creatorcontrib>MARR DEBORAH T ; VAN DOREN STEPHEN R ; SHEFFIELD DAVID B ; SANKARAN RAJESH M ; MCDONNELL NIALL D ; VENKATESH GANESH ; O'HANLON MICHAEL A ; CORBAL JESUS ; YAMADA KOICHI ; NURVITADHI ERIKO ; VALENTINE ROBERT ; MANLEY DWIGHT P ; BRADFORD DENNIS R ; GLOSSOP KENT D ; CARTER NICHOLAS P ; NEIGER GILBERT ; COOK JEFFREY J ; MOSUR LOKPRAVEEN B ; MISHRA ASIT K ; RANGANATHAN NARAYAN ; CHARNEY MARK J ; GROCHOWSKI EDWARD T ; GRECO RICHARD J ; NUZMAN JOSEPH ; PEARCE JONATHAN D ; FLETCHER THOMAS D ; CAPRIOLI PAUL ; DRYSDALE TRACY GARRETT</creatorcontrib><description>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들의 실시예들이 설명된다. 일부 실시예들에서, 하드웨어 이종 스케줄러는 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 상에서의 실행을 위해 명령어들을 디스패치하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소에 의해 처리될 코드 조각에 대응하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 중의 적어도 하나의 이종 처리 요소에 대한 고유 명령어들이다.
The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.</description><language>kor</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190809&DB=EPODOC&CC=KR&NR=20190093568A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190809&DB=EPODOC&CC=KR&NR=20190093568A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MARR DEBORAH T</creatorcontrib><creatorcontrib>VAN DOREN STEPHEN R</creatorcontrib><creatorcontrib>SHEFFIELD DAVID B</creatorcontrib><creatorcontrib>SANKARAN RAJESH M</creatorcontrib><creatorcontrib>MCDONNELL NIALL D</creatorcontrib><creatorcontrib>VENKATESH GANESH</creatorcontrib><creatorcontrib>O'HANLON MICHAEL A</creatorcontrib><creatorcontrib>CORBAL JESUS</creatorcontrib><creatorcontrib>YAMADA KOICHI</creatorcontrib><creatorcontrib>NURVITADHI ERIKO</creatorcontrib><creatorcontrib>VALENTINE ROBERT</creatorcontrib><creatorcontrib>MANLEY DWIGHT P</creatorcontrib><creatorcontrib>BRADFORD DENNIS R</creatorcontrib><creatorcontrib>GLOSSOP KENT D</creatorcontrib><creatorcontrib>CARTER NICHOLAS P</creatorcontrib><creatorcontrib>NEIGER GILBERT</creatorcontrib><creatorcontrib>COOK JEFFREY J</creatorcontrib><creatorcontrib>MOSUR LOKPRAVEEN B</creatorcontrib><creatorcontrib>MISHRA ASIT K</creatorcontrib><creatorcontrib>RANGANATHAN NARAYAN</creatorcontrib><creatorcontrib>CHARNEY MARK J</creatorcontrib><creatorcontrib>GROCHOWSKI EDWARD T</creatorcontrib><creatorcontrib>GRECO RICHARD J</creatorcontrib><creatorcontrib>NUZMAN JOSEPH</creatorcontrib><creatorcontrib>PEARCE JONATHAN D</creatorcontrib><creatorcontrib>FLETCHER THOMAS D</creatorcontrib><creatorcontrib>CAPRIOLI PAUL</creatorcontrib><creatorcontrib>DRYSDALE TRACY GARRETT</creatorcontrib><title>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들</title><description>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들의 실시예들이 설명된다. 일부 실시예들에서, 하드웨어 이종 스케줄러는 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 상에서의 실행을 위해 명령어들을 디스패치하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소에 의해 처리될 코드 조각에 대응하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 중의 적어도 하나의 이종 처리 요소에 대한 고유 명령어들이다.
The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHB8M3fLm0WtCm92b3k7ecXbntY3c1sU3sxpeTt1jsKb7jlvupa8bZ3zevISHYXXG1a-3jQVyuxXeDNv6ZudM4BcHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oS7x1kZGBoaWBgaWxqZuFoTJwqAFE3Q-c</recordid><startdate>20190809</startdate><enddate>20190809</enddate><creator>MARR DEBORAH T</creator><creator>VAN DOREN STEPHEN R</creator><creator>SHEFFIELD DAVID B</creator><creator>SANKARAN RAJESH M</creator><creator>MCDONNELL NIALL D</creator><creator>VENKATESH GANESH</creator><creator>O'HANLON MICHAEL A</creator><creator>CORBAL JESUS</creator><creator>YAMADA KOICHI</creator><creator>NURVITADHI ERIKO</creator><creator>VALENTINE ROBERT</creator><creator>MANLEY DWIGHT P</creator><creator>BRADFORD DENNIS R</creator><creator>GLOSSOP KENT D</creator><creator>CARTER NICHOLAS P</creator><creator>NEIGER GILBERT</creator><creator>COOK JEFFREY J</creator><creator>MOSUR LOKPRAVEEN B</creator><creator>MISHRA ASIT K</creator><creator>RANGANATHAN NARAYAN</creator><creator>CHARNEY MARK J</creator><creator>GROCHOWSKI EDWARD T</creator><creator>GRECO RICHARD J</creator><creator>NUZMAN JOSEPH</creator><creator>PEARCE JONATHAN D</creator><creator>FLETCHER THOMAS D</creator><creator>CAPRIOLI PAUL</creator><creator>DRYSDALE TRACY GARRETT</creator><scope>EVB</scope></search><sort><creationdate>20190809</creationdate><title>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들</title><author>MARR DEBORAH T ; VAN DOREN STEPHEN R ; SHEFFIELD DAVID B ; SANKARAN RAJESH M ; MCDONNELL NIALL D ; VENKATESH GANESH ; O'HANLON MICHAEL A ; CORBAL JESUS ; YAMADA KOICHI ; NURVITADHI ERIKO ; VALENTINE ROBERT ; MANLEY DWIGHT P ; BRADFORD DENNIS R ; GLOSSOP KENT D ; CARTER NICHOLAS P ; NEIGER GILBERT ; COOK JEFFREY J ; MOSUR LOKPRAVEEN B ; MISHRA ASIT K ; RANGANATHAN NARAYAN ; CHARNEY MARK J ; GROCHOWSKI EDWARD T ; GRECO RICHARD J ; NUZMAN JOSEPH ; PEARCE JONATHAN D ; FLETCHER THOMAS D ; CAPRIOLI PAUL ; DRYSDALE TRACY GARRETT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190093568A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>kor</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MARR DEBORAH T</creatorcontrib><creatorcontrib>VAN DOREN STEPHEN R</creatorcontrib><creatorcontrib>SHEFFIELD DAVID B</creatorcontrib><creatorcontrib>SANKARAN RAJESH M</creatorcontrib><creatorcontrib>MCDONNELL NIALL D</creatorcontrib><creatorcontrib>VENKATESH GANESH</creatorcontrib><creatorcontrib>O'HANLON MICHAEL A</creatorcontrib><creatorcontrib>CORBAL JESUS</creatorcontrib><creatorcontrib>YAMADA KOICHI</creatorcontrib><creatorcontrib>NURVITADHI ERIKO</creatorcontrib><creatorcontrib>VALENTINE ROBERT</creatorcontrib><creatorcontrib>MANLEY DWIGHT P</creatorcontrib><creatorcontrib>BRADFORD DENNIS R</creatorcontrib><creatorcontrib>GLOSSOP KENT D</creatorcontrib><creatorcontrib>CARTER NICHOLAS P</creatorcontrib><creatorcontrib>NEIGER GILBERT</creatorcontrib><creatorcontrib>COOK JEFFREY J</creatorcontrib><creatorcontrib>MOSUR LOKPRAVEEN B</creatorcontrib><creatorcontrib>MISHRA ASIT K</creatorcontrib><creatorcontrib>RANGANATHAN NARAYAN</creatorcontrib><creatorcontrib>CHARNEY MARK J</creatorcontrib><creatorcontrib>GROCHOWSKI EDWARD T</creatorcontrib><creatorcontrib>GRECO RICHARD J</creatorcontrib><creatorcontrib>NUZMAN JOSEPH</creatorcontrib><creatorcontrib>PEARCE JONATHAN D</creatorcontrib><creatorcontrib>FLETCHER THOMAS D</creatorcontrib><creatorcontrib>CAPRIOLI PAUL</creatorcontrib><creatorcontrib>DRYSDALE TRACY GARRETT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MARR DEBORAH T</au><au>VAN DOREN STEPHEN R</au><au>SHEFFIELD DAVID B</au><au>SANKARAN RAJESH M</au><au>MCDONNELL NIALL D</au><au>VENKATESH GANESH</au><au>O'HANLON MICHAEL A</au><au>CORBAL JESUS</au><au>YAMADA KOICHI</au><au>NURVITADHI ERIKO</au><au>VALENTINE ROBERT</au><au>MANLEY DWIGHT P</au><au>BRADFORD DENNIS R</au><au>GLOSSOP KENT D</au><au>CARTER NICHOLAS P</au><au>NEIGER GILBERT</au><au>COOK JEFFREY J</au><au>MOSUR LOKPRAVEEN B</au><au>MISHRA ASIT K</au><au>RANGANATHAN NARAYAN</au><au>CHARNEY MARK J</au><au>GROCHOWSKI EDWARD T</au><au>GRECO RICHARD J</au><au>NUZMAN JOSEPH</au><au>PEARCE JONATHAN D</au><au>FLETCHER THOMAS D</au><au>CAPRIOLI PAUL</au><au>DRYSDALE TRACY GARRETT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들</title><date>2019-08-09</date><risdate>2019</risdate><abstract>이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들의 실시예들이 설명된다. 일부 실시예들에서, 하드웨어 이종 스케줄러는 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 상에서의 실행을 위해 명령어들을 디스패치하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소에 의해 처리될 코드 조각에 대응하고, 명령어들은 복수의 이종 처리 요소들 중 하나 이상의 이종 처리 요소 중의 적어도 하나의 이종 처리 요소에 대한 고유 명령어들이다.
The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | 이종 컴퓨팅을 위한 시스템들, 방법들, 및 장치들 |
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