CMOS FIELD EFFECT TRANSISTOR CMOS SYSTEM ON CHIP AND METHOD OF MANUFACTURING THE SAME
Disclosed is a CMOS system on a chip including a series of partial gate-all-around field effect transistors (GAA FETs). Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions formed on both sides of the fin, a dielectric separation region including a dielectr...
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creator | OBRADOVIC BORNA JOSIP SENGUPTA RWIK POURGHADERI MOHAMMAD ALI RODDER MARK S PALLE DHARMENDAR REDDY |
description | Disclosed is a CMOS system on a chip including a series of partial gate-all-around field effect transistors (GAA FETs). Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions formed on both sides of the fin, a dielectric separation region including a dielectric material formed between first and second channel regions, a gate stack formed on the fin, and a pair of sidewall spacers formed on both sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of each of the sidewall spacers. The length of a portion of the dielectric separation region of one of the partial GAA FETs is different from the length of a portion of the dielectric separation region of another one of the partial GAA FETs. Thus, the maximum performance can be achieved at the lowest dynamic power.
일련의 부분 게이트-올-어라운드 전계효과 트랜지스터들을 포함하는 CMOS 시스템온칩이 개시된다. 각각의 부분 GAA FET은 채널영역 스택을 포함하는 핀, 핀의 양측에 형성된 소스영역 및 드레인영역, 제1 채널영역 및 제2 채널영역 사이에 형성된 유전물질을 포함하는 유전체 분리영역, 핀 상에 형성된 게이트스택, 및 게이트스택의 양측에 형성된 한 쌍의 측벽 스페이서를 포함한다. 유전체 분리영역의 일부분은 유전체 분리영역의 외측 에지에서부터 각각의 측벽 스페이서의 내측 에지까지의 길이를 갖는다. 부분 GAA FET들 중 하나의 유전체 분리영역의 일부분의 길이는 부분 GAA FET들 중 다른 하나의 유전체 분리영역의 일부분의 길이와 상이하다. |
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일련의 부분 게이트-올-어라운드 전계효과 트랜지스터들을 포함하는 CMOS 시스템온칩이 개시된다. 각각의 부분 GAA FET은 채널영역 스택을 포함하는 핀, 핀의 양측에 형성된 소스영역 및 드레인영역, 제1 채널영역 및 제2 채널영역 사이에 형성된 유전물질을 포함하는 유전체 분리영역, 핀 상에 형성된 게이트스택, 및 게이트스택의 양측에 형성된 한 쌍의 측벽 스페이서를 포함한다. 유전체 분리영역의 일부분은 유전체 분리영역의 외측 에지에서부터 각각의 측벽 스페이서의 내측 에지까지의 길이를 갖는다. 부분 GAA FET들 중 하나의 유전체 분리영역의 일부분의 길이는 부분 GAA FET들 중 다른 하나의 유전체 분리영역의 일부분의 길이와 상이하다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190619&DB=EPODOC&CC=KR&NR=20190069294A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190619&DB=EPODOC&CC=KR&NR=20190069294A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OBRADOVIC BORNA JOSIP</creatorcontrib><creatorcontrib>SENGUPTA RWIK</creatorcontrib><creatorcontrib>POURGHADERI MOHAMMAD ALI</creatorcontrib><creatorcontrib>RODDER MARK S</creatorcontrib><creatorcontrib>PALLE DHARMENDAR REDDY</creatorcontrib><title>CMOS FIELD EFFECT TRANSISTOR CMOS SYSTEM ON CHIP AND METHOD OF MANUFACTURING THE SAME</title><description>Disclosed is a CMOS system on a chip including a series of partial gate-all-around field effect transistors (GAA FETs). Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions formed on both sides of the fin, a dielectric separation region including a dielectric material formed between first and second channel regions, a gate stack formed on the fin, and a pair of sidewall spacers formed on both sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of each of the sidewall spacers. The length of a portion of the dielectric separation region of one of the partial GAA FETs is different from the length of a portion of the dielectric separation region of another one of the partial GAA FETs. Thus, the maximum performance can be achieved at the lowest dynamic power.
일련의 부분 게이트-올-어라운드 전계효과 트랜지스터들을 포함하는 CMOS 시스템온칩이 개시된다. 각각의 부분 GAA FET은 채널영역 스택을 포함하는 핀, 핀의 양측에 형성된 소스영역 및 드레인영역, 제1 채널영역 및 제2 채널영역 사이에 형성된 유전물질을 포함하는 유전체 분리영역, 핀 상에 형성된 게이트스택, 및 게이트스택의 양측에 형성된 한 쌍의 측벽 스페이서를 포함한다. 유전체 분리영역의 일부분은 유전체 분리영역의 외측 에지에서부터 각각의 측벽 스페이서의 내측 에지까지의 길이를 갖는다. 부분 GAA FET들 중 하나의 유전체 분리영역의 일부분의 길이는 부분 GAA FET들 중 다른 하나의 유전체 분리영역의 일부분의 길이와 상이하다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKAjEQQNE0FqLeYcBaiKsIKUMyY4ImkWRSWC2LxEp0Yb0_gngAq1-8PxfVhFSAPJ4tIBEaBs46Fl84ZfhiuRbGACmCcf4COloIyC5ZSARBx0racM0-HoEdQtEBl2J2Hx5TW_26EGtCNm7TxlffpnG4tWd796fcya2S8qA6tde7_64P91QxBA</recordid><startdate>20190619</startdate><enddate>20190619</enddate><creator>OBRADOVIC BORNA JOSIP</creator><creator>SENGUPTA RWIK</creator><creator>POURGHADERI MOHAMMAD ALI</creator><creator>RODDER MARK S</creator><creator>PALLE DHARMENDAR REDDY</creator><scope>EVB</scope></search><sort><creationdate>20190619</creationdate><title>CMOS FIELD EFFECT TRANSISTOR CMOS SYSTEM ON CHIP AND METHOD OF MANUFACTURING THE SAME</title><author>OBRADOVIC BORNA JOSIP ; SENGUPTA RWIK ; POURGHADERI MOHAMMAD ALI ; RODDER MARK S ; PALLE DHARMENDAR REDDY</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190069294A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OBRADOVIC BORNA JOSIP</creatorcontrib><creatorcontrib>SENGUPTA RWIK</creatorcontrib><creatorcontrib>POURGHADERI MOHAMMAD ALI</creatorcontrib><creatorcontrib>RODDER MARK S</creatorcontrib><creatorcontrib>PALLE DHARMENDAR REDDY</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OBRADOVIC BORNA JOSIP</au><au>SENGUPTA RWIK</au><au>POURGHADERI MOHAMMAD ALI</au><au>RODDER MARK S</au><au>PALLE DHARMENDAR REDDY</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CMOS FIELD EFFECT TRANSISTOR CMOS SYSTEM ON CHIP AND METHOD OF MANUFACTURING THE SAME</title><date>2019-06-19</date><risdate>2019</risdate><abstract>Disclosed is a CMOS system on a chip including a series of partial gate-all-around field effect transistors (GAA FETs). Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions formed on both sides of the fin, a dielectric separation region including a dielectric material formed between first and second channel regions, a gate stack formed on the fin, and a pair of sidewall spacers formed on both sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of each of the sidewall spacers. The length of a portion of the dielectric separation region of one of the partial GAA FETs is different from the length of a portion of the dielectric separation region of another one of the partial GAA FETs. Thus, the maximum performance can be achieved at the lowest dynamic power.
일련의 부분 게이트-올-어라운드 전계효과 트랜지스터들을 포함하는 CMOS 시스템온칩이 개시된다. 각각의 부분 GAA FET은 채널영역 스택을 포함하는 핀, 핀의 양측에 형성된 소스영역 및 드레인영역, 제1 채널영역 및 제2 채널영역 사이에 형성된 유전물질을 포함하는 유전체 분리영역, 핀 상에 형성된 게이트스택, 및 게이트스택의 양측에 형성된 한 쌍의 측벽 스페이서를 포함한다. 유전체 분리영역의 일부분은 유전체 분리영역의 외측 에지에서부터 각각의 측벽 스페이서의 내측 에지까지의 길이를 갖는다. 부분 GAA FET들 중 하나의 유전체 분리영역의 일부분의 길이는 부분 GAA FET들 중 다른 하나의 유전체 분리영역의 일부분의 길이와 상이하다.</abstract><oa>free_for_read</oa></addata></record> |
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title | CMOS FIELD EFFECT TRANSISTOR CMOS SYSTEM ON CHIP AND METHOD OF MANUFACTURING THE SAME |
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