SEMICONDUCTOR PACKAGE WITH AIR CAVITY
Embodiments relating to a chip-package and corresponding manufacturing methods are provided. In an embodiment relating to a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a secon...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; kor |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | REISS WERNER SCHMALZL STEFAN LEE CHEE HONG CHIN KON HOE TUAZON BERNARDEZ APRIL COLEEN LIEW SOON LEE OTHMAN NURFARENA CHUA KOK YAU KUEK HSIEH TING CHIANG CHAU FATT BAKAR ROSLIE SAINI BIN ABDUL WAHID JUNNY CHONG HOCK HENG POK PEI LUAN |
| description | Embodiments relating to a chip-package and corresponding manufacturing methods are provided. In an embodiment relating to a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation having a first portion which at least partially encloses the first chip on the first side of the carrier, and a second portion which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and a conductive material which at least partly covers a sidewall of the via in the first or the second portion of the encapsulation, to enable the carrier to be in electrical contact with the first side or the second side. Thus, improved chip package is provided.
칩 패키지 및 그에 대응하는 제조 방법에 관한 실시예들이 제공된다. 칩 패키지에 관한 일 실시예에서, 칩 패키지는, 제 1 측면 및 제 1 측면에 대향하는 제 2 측면을 갖는 캐리어와, 캐리어의 제 1 측면에 결합된 제 1 칩과, 캐리어의 제 2 측면에 결합된 제 2 칩과, 캐리어의 제 1 측면 상에 제 1 칩을 적어도 부분적으로 인클로징하는 제 1 부분 및 캐리어의 제 2 측면 상에 제 2 칩을 적어도 부분적으로 인클로징하는 제 2 부분을 갖는 인캡슐레이션과, 인캡슐레이션의 제 1 부분, 캐리어 및 인캡슐레이션의 제 2 부분을 통과하여 연장되는 비아와, 제 1 측면 또는 제 2 측면 중 하나에 캐리어를 전기적으로 접촉시키기 위해 인캡슐레이션의 제 1 부분 또는 제 2 부분 내에 비아의 측벽을 적어도 부분적으로 덮는 도전성 물질을 포함한다. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20190068468A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20190068468A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20190068468A3</originalsourceid><addsrcrecordid>eNrjZFANdvX1dPb3cwl1DvEPUghwdPZ2dHdVCPcM8VBw9AxScHYM8wyJ5GFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgaGlgYGZhYmZhaOxsSpAgAtUyQz</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE WITH AIR CAVITY</title><source>esp@cenet</source><creator>REISS WERNER ; SCHMALZL STEFAN ; LEE CHEE HONG ; CHIN KON HOE ; TUAZON BERNARDEZ APRIL COLEEN ; LIEW SOON LEE ; OTHMAN NURFARENA ; CHUA KOK YAU ; KUEK HSIEH TING ; CHIANG CHAU FATT ; BAKAR ROSLIE SAINI BIN ; ABDUL WAHID JUNNY ; CHONG HOCK HENG ; POK PEI LUAN</creator><creatorcontrib>REISS WERNER ; SCHMALZL STEFAN ; LEE CHEE HONG ; CHIN KON HOE ; TUAZON BERNARDEZ APRIL COLEEN ; LIEW SOON LEE ; OTHMAN NURFARENA ; CHUA KOK YAU ; KUEK HSIEH TING ; CHIANG CHAU FATT ; BAKAR ROSLIE SAINI BIN ; ABDUL WAHID JUNNY ; CHONG HOCK HENG ; POK PEI LUAN</creatorcontrib><description>Embodiments relating to a chip-package and corresponding manufacturing methods are provided. In an embodiment relating to a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation having a first portion which at least partially encloses the first chip on the first side of the carrier, and a second portion which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and a conductive material which at least partly covers a sidewall of the via in the first or the second portion of the encapsulation, to enable the carrier to be in electrical contact with the first side or the second side. Thus, improved chip package is provided.
칩 패키지 및 그에 대응하는 제조 방법에 관한 실시예들이 제공된다. 칩 패키지에 관한 일 실시예에서, 칩 패키지는, 제 1 측면 및 제 1 측면에 대향하는 제 2 측면을 갖는 캐리어와, 캐리어의 제 1 측면에 결합된 제 1 칩과, 캐리어의 제 2 측면에 결합된 제 2 칩과, 캐리어의 제 1 측면 상에 제 1 칩을 적어도 부분적으로 인클로징하는 제 1 부분 및 캐리어의 제 2 측면 상에 제 2 칩을 적어도 부분적으로 인클로징하는 제 2 부분을 갖는 인캡슐레이션과, 인캡슐레이션의 제 1 부분, 캐리어 및 인캡슐레이션의 제 2 부분을 통과하여 연장되는 비아와, 제 1 측면 또는 제 2 측면 중 하나에 캐리어를 전기적으로 접촉시키기 위해 인캡슐레이션의 제 1 부분 또는 제 2 부분 내에 비아의 측벽을 적어도 부분적으로 덮는 도전성 물질을 포함한다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190618&DB=EPODOC&CC=KR&NR=20190068468A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190618&DB=EPODOC&CC=KR&NR=20190068468A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>REISS WERNER</creatorcontrib><creatorcontrib>SCHMALZL STEFAN</creatorcontrib><creatorcontrib>LEE CHEE HONG</creatorcontrib><creatorcontrib>CHIN KON HOE</creatorcontrib><creatorcontrib>TUAZON BERNARDEZ APRIL COLEEN</creatorcontrib><creatorcontrib>LIEW SOON LEE</creatorcontrib><creatorcontrib>OTHMAN NURFARENA</creatorcontrib><creatorcontrib>CHUA KOK YAU</creatorcontrib><creatorcontrib>KUEK HSIEH TING</creatorcontrib><creatorcontrib>CHIANG CHAU FATT</creatorcontrib><creatorcontrib>BAKAR ROSLIE SAINI BIN</creatorcontrib><creatorcontrib>ABDUL WAHID JUNNY</creatorcontrib><creatorcontrib>CHONG HOCK HENG</creatorcontrib><creatorcontrib>POK PEI LUAN</creatorcontrib><title>SEMICONDUCTOR PACKAGE WITH AIR CAVITY</title><description>Embodiments relating to a chip-package and corresponding manufacturing methods are provided. In an embodiment relating to a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation having a first portion which at least partially encloses the first chip on the first side of the carrier, and a second portion which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and a conductive material which at least partly covers a sidewall of the via in the first or the second portion of the encapsulation, to enable the carrier to be in electrical contact with the first side or the second side. Thus, improved chip package is provided.
칩 패키지 및 그에 대응하는 제조 방법에 관한 실시예들이 제공된다. 칩 패키지에 관한 일 실시예에서, 칩 패키지는, 제 1 측면 및 제 1 측면에 대향하는 제 2 측면을 갖는 캐리어와, 캐리어의 제 1 측면에 결합된 제 1 칩과, 캐리어의 제 2 측면에 결합된 제 2 칩과, 캐리어의 제 1 측면 상에 제 1 칩을 적어도 부분적으로 인클로징하는 제 1 부분 및 캐리어의 제 2 측면 상에 제 2 칩을 적어도 부분적으로 인클로징하는 제 2 부분을 갖는 인캡슐레이션과, 인캡슐레이션의 제 1 부분, 캐리어 및 인캡슐레이션의 제 2 부분을 통과하여 연장되는 비아와, 제 1 측면 또는 제 2 측면 중 하나에 캐리어를 전기적으로 접촉시키기 위해 인캡슐레이션의 제 1 부분 또는 제 2 부분 내에 비아의 측벽을 적어도 부분적으로 덮는 도전성 물질을 포함한다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFANdvX1dPb3cwl1DvEPUghwdPZ2dHdVCPcM8VBw9AxScHYM8wyJ5GFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgaGlgYGZhYmZhaOxsSpAgAtUyQz</recordid><startdate>20190618</startdate><enddate>20190618</enddate><creator>REISS WERNER</creator><creator>SCHMALZL STEFAN</creator><creator>LEE CHEE HONG</creator><creator>CHIN KON HOE</creator><creator>TUAZON BERNARDEZ APRIL COLEEN</creator><creator>LIEW SOON LEE</creator><creator>OTHMAN NURFARENA</creator><creator>CHUA KOK YAU</creator><creator>KUEK HSIEH TING</creator><creator>CHIANG CHAU FATT</creator><creator>BAKAR ROSLIE SAINI BIN</creator><creator>ABDUL WAHID JUNNY</creator><creator>CHONG HOCK HENG</creator><creator>POK PEI LUAN</creator><scope>EVB</scope></search><sort><creationdate>20190618</creationdate><title>SEMICONDUCTOR PACKAGE WITH AIR CAVITY</title><author>REISS WERNER ; SCHMALZL STEFAN ; LEE CHEE HONG ; CHIN KON HOE ; TUAZON BERNARDEZ APRIL COLEEN ; LIEW SOON LEE ; OTHMAN NURFARENA ; CHUA KOK YAU ; KUEK HSIEH TING ; CHIANG CHAU FATT ; BAKAR ROSLIE SAINI BIN ; ABDUL WAHID JUNNY ; CHONG HOCK HENG ; POK PEI LUAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190068468A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>REISS WERNER</creatorcontrib><creatorcontrib>SCHMALZL STEFAN</creatorcontrib><creatorcontrib>LEE CHEE HONG</creatorcontrib><creatorcontrib>CHIN KON HOE</creatorcontrib><creatorcontrib>TUAZON BERNARDEZ APRIL COLEEN</creatorcontrib><creatorcontrib>LIEW SOON LEE</creatorcontrib><creatorcontrib>OTHMAN NURFARENA</creatorcontrib><creatorcontrib>CHUA KOK YAU</creatorcontrib><creatorcontrib>KUEK HSIEH TING</creatorcontrib><creatorcontrib>CHIANG CHAU FATT</creatorcontrib><creatorcontrib>BAKAR ROSLIE SAINI BIN</creatorcontrib><creatorcontrib>ABDUL WAHID JUNNY</creatorcontrib><creatorcontrib>CHONG HOCK HENG</creatorcontrib><creatorcontrib>POK PEI LUAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>REISS WERNER</au><au>SCHMALZL STEFAN</au><au>LEE CHEE HONG</au><au>CHIN KON HOE</au><au>TUAZON BERNARDEZ APRIL COLEEN</au><au>LIEW SOON LEE</au><au>OTHMAN NURFARENA</au><au>CHUA KOK YAU</au><au>KUEK HSIEH TING</au><au>CHIANG CHAU FATT</au><au>BAKAR ROSLIE SAINI BIN</au><au>ABDUL WAHID JUNNY</au><au>CHONG HOCK HENG</au><au>POK PEI LUAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE WITH AIR CAVITY</title><date>2019-06-18</date><risdate>2019</risdate><abstract>Embodiments relating to a chip-package and corresponding manufacturing methods are provided. In an embodiment relating to a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation having a first portion which at least partially encloses the first chip on the first side of the carrier, and a second portion which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and a conductive material which at least partly covers a sidewall of the via in the first or the second portion of the encapsulation, to enable the carrier to be in electrical contact with the first side or the second side. Thus, improved chip package is provided.
칩 패키지 및 그에 대응하는 제조 방법에 관한 실시예들이 제공된다. 칩 패키지에 관한 일 실시예에서, 칩 패키지는, 제 1 측면 및 제 1 측면에 대향하는 제 2 측면을 갖는 캐리어와, 캐리어의 제 1 측면에 결합된 제 1 칩과, 캐리어의 제 2 측면에 결합된 제 2 칩과, 캐리어의 제 1 측면 상에 제 1 칩을 적어도 부분적으로 인클로징하는 제 1 부분 및 캐리어의 제 2 측면 상에 제 2 칩을 적어도 부분적으로 인클로징하는 제 2 부분을 갖는 인캡슐레이션과, 인캡슐레이션의 제 1 부분, 캐리어 및 인캡슐레이션의 제 2 부분을 통과하여 연장되는 비아와, 제 1 측면 또는 제 2 측면 중 하나에 캐리어를 전기적으로 접촉시키기 위해 인캡슐레이션의 제 1 부분 또는 제 2 부분 내에 비아의 측벽을 적어도 부분적으로 덮는 도전성 물질을 포함한다.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; kor |
| recordid | cdi_epo_espacenet_KR20190068468A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR PACKAGE WITH AIR CAVITY |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T05%3A40%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=REISS%20WERNER&rft.date=2019-06-18&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20190068468A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |