3 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A three-dimensional semiconductor memory device and a method of manufacturing the same are provided. The three-dimensional semiconductor memory device includes: a substrate including a cell array region and a connection region; an electrode structure including electrodes and insulating films alterna...

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Hauptverfasser: NAM, PHIL OUK, AHN, JAE YOUNG, LEE, SANG SOO
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AHN, JAE YOUNG
LEE, SANG SOO
description A three-dimensional semiconductor memory device and a method of manufacturing the same are provided. The three-dimensional semiconductor memory device includes: a substrate including a cell array region and a connection region; an electrode structure including electrodes and insulating films alternately stacked along a first direction perpendicular to the upper surface of the substrate, wherein the electrode structure has a step structure in the connection region; and contact plugs individually connected to the ends of the electrodes in the connection region. As the distance between the substrate and the electrodes in the first direction increases, the distances between the bottom surfaces of the contact plugs and the upper surfaces of the electrodes connected thereto may increase. It is possible to increase the integration of the three-dimensional semiconductor memory device. 3차원 반도체 메모리 장치 및 그 제조 방법이 제공된다. 3차원 반도체 메모리 장치는 셀 어레이 영역 및 연결 영역을 포함하는 기판; 상기 기판의 상면에 대해 수직하는 제 1 방향을 따라 번갈아 적층된 전극들 및 절연막들을 포함하는 전극 구조체로서, 상기 전극 구조체는 상기 연결 영역에서 계단 구조를 갖는 것; 및 상기 연결 영역에서 상기 전극들의 단부들에 각각 접속되는 콘택 플러그들을 포함하되, 상기 기판과 상기 전극들 간의 상기 제 1 방향으로의 거리가 증가할수록, 상기 콘택 플러그들의 바닥면들과 이에 연결되는 상기 전극들의 상면들 간의 거리들이 증가할 수 있다.
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It is possible to increase the integration of the three-dimensional semiconductor memory device. 3차원 반도체 메모리 장치 및 그 제조 방법이 제공된다. 3차원 반도체 메모리 장치는 셀 어레이 영역 및 연결 영역을 포함하는 기판; 상기 기판의 상면에 대해 수직하는 제 1 방향을 따라 번갈아 적층된 전극들 및 절연막들을 포함하는 전극 구조체로서, 상기 전극 구조체는 상기 연결 영역에서 계단 구조를 갖는 것; 및 상기 연결 영역에서 상기 전극들의 단부들에 각각 접속되는 콘택 플러그들을 포함하되, 상기 기판과 상기 전극들 간의 상기 제 1 방향으로의 거리가 증가할수록, 상기 콘택 플러그들의 바닥면들과 이에 연결되는 상기 전극들의 상면들 간의 거리들이 증가할 수 있다.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKwjAUALM4iPoPD5wLaStCx2fyYh42CSTRtRSJk2ih_j928AOcDo7j1qJvIdtIVGl25BMHjz0kcqyC11eVQwRNN1YE6DU4yjZoMIs1eIqsMLM_LweChI62YvUYn3PZ_bgRe0NZ2apM76HM03gvr_IZLrGRdSelPNaHBtv_qi8-OC5X</recordid><startdate>20190117</startdate><enddate>20190117</enddate><creator>NAM, PHIL OUK</creator><creator>AHN, JAE YOUNG</creator><creator>LEE, SANG SOO</creator><scope>EVB</scope></search><sort><creationdate>20190117</creationdate><title>3 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME</title><author>NAM, PHIL OUK ; AHN, JAE YOUNG ; LEE, SANG SOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20190006142A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2019</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>NAM, PHIL OUK</creatorcontrib><creatorcontrib>AHN, JAE YOUNG</creatorcontrib><creatorcontrib>LEE, SANG SOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAM, PHIL OUK</au><au>AHN, JAE YOUNG</au><au>LEE, SANG SOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>3 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME</title><date>2019-01-17</date><risdate>2019</risdate><abstract>A three-dimensional semiconductor memory device and a method of manufacturing the same are provided. The three-dimensional semiconductor memory device includes: a substrate including a cell array region and a connection region; an electrode structure including electrodes and insulating films alternately stacked along a first direction perpendicular to the upper surface of the substrate, wherein the electrode structure has a step structure in the connection region; and contact plugs individually connected to the ends of the electrodes in the connection region. As the distance between the substrate and the electrodes in the first direction increases, the distances between the bottom surfaces of the contact plugs and the upper surfaces of the electrodes connected thereto may increase. It is possible to increase the integration of the three-dimensional semiconductor memory device. 3차원 반도체 메모리 장치 및 그 제조 방법이 제공된다. 3차원 반도체 메모리 장치는 셀 어레이 영역 및 연결 영역을 포함하는 기판; 상기 기판의 상면에 대해 수직하는 제 1 방향을 따라 번갈아 적층된 전극들 및 절연막들을 포함하는 전극 구조체로서, 상기 전극 구조체는 상기 연결 영역에서 계단 구조를 갖는 것; 및 상기 연결 영역에서 상기 전극들의 단부들에 각각 접속되는 콘택 플러그들을 포함하되, 상기 기판과 상기 전극들 간의 상기 제 1 방향으로의 거리가 증가할수록, 상기 콘택 플러그들의 바닥면들과 이에 연결되는 상기 전극들의 상면들 간의 거리들이 증가할 수 있다.</abstract><oa>free_for_read</oa></addata></record>
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title 3 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
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