MANUFACTURING METHOD FOR SILICON NANOWIRES INTEGRATED WITH MICROSCALE SILICON STRUCTURES
Embodiments of the present invention relate to a method for manufacturing a silicon nanowire integrated with a microscale silicon structure. The method comprises the steps of: (S100) forming a first oxide film on a substrate; (S200) etching the substrate to form a recessed region for separating a na...
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| creator | CHO, DONG IL YOO, HYUNG JUNG SHIN, JONG YOON JANG, SEO HYEONG |
| description | Embodiments of the present invention relate to a method for manufacturing a silicon nanowire integrated with a microscale silicon structure. The method comprises the steps of: (S100) forming a first oxide film on a substrate; (S200) etching the substrate to form a recessed region for separating a nanowire region and a microscale structure region using the first oxide film as a mask; (S300) forming a second oxide film on the etched substrate through a thermal oxidation process; (S400) removing the second oxide film on a bottom surface of the recessed; and (S500) performing wet etching on the substrate to float a nanowire. Therefore, the method may individually control a width and thickness of the nanowire.
실시예들은 기판 상에 제1 산화막을 형성하는 단계(S100), 제1 산화막을 마스크로 이용하여, 나노 와이어 영역과 마이크로 스케일 구조물 영역을 구분하는 함몰영역이 생성되도록 기판을 식각하는 단계(S200), 식각된 기판 상에 열산화 공정을 통해 제2 산화막을 형성하는 단계(S300), 상기 함몰영역의 바닥면의 제2 산화막을 제거하는 단계(S400) 및 나노 와이어가 부유되도록, 상기 기판을 습식 식각하는 단계(S500)를 포함하는 마이크로 스케일 실리콘 구조물과 통합되는 실리콘 나노 와이어 제조방법에 관련된다. |
| format | Patent |
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실시예들은 기판 상에 제1 산화막을 형성하는 단계(S100), 제1 산화막을 마스크로 이용하여, 나노 와이어 영역과 마이크로 스케일 구조물 영역을 구분하는 함몰영역이 생성되도록 기판을 식각하는 단계(S200), 식각된 기판 상에 열산화 공정을 통해 제2 산화막을 형성하는 단계(S300), 상기 함몰영역의 바닥면의 제2 산화막을 제거하는 단계(S400) 및 나노 와이어가 부유되도록, 상기 기판을 습식 식각하는 단계(S500)를 포함하는 마이크로 스케일 실리콘 구조물과 통합되는 실리콘 나노 와이어 제조방법에 관련된다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181211&DB=EPODOC&CC=KR&NR=20180131889A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181211&DB=EPODOC&CC=KR&NR=20180131889A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHO, DONG IL</creatorcontrib><creatorcontrib>YOO, HYUNG JUNG</creatorcontrib><creatorcontrib>SHIN, JONG YOON</creatorcontrib><creatorcontrib>JANG, SEO HYEONG</creatorcontrib><title>MANUFACTURING METHOD FOR SILICON NANOWIRES INTEGRATED WITH MICROSCALE SILICON STRUCTURES</title><description>Embodiments of the present invention relate to a method for manufacturing a silicon nanowire integrated with a microscale silicon structure. The method comprises the steps of: (S100) forming a first oxide film on a substrate; (S200) etching the substrate to form a recessed region for separating a nanowire region and a microscale structure region using the first oxide film as a mask; (S300) forming a second oxide film on the etched substrate through a thermal oxidation process; (S400) removing the second oxide film on a bottom surface of the recessed; and (S500) performing wet etching on the substrate to float a nanowire. Therefore, the method may individually control a width and thickness of the nanowire.
실시예들은 기판 상에 제1 산화막을 형성하는 단계(S100), 제1 산화막을 마스크로 이용하여, 나노 와이어 영역과 마이크로 스케일 구조물 영역을 구분하는 함몰영역이 생성되도록 기판을 식각하는 단계(S200), 식각된 기판 상에 열산화 공정을 통해 제2 산화막을 형성하는 단계(S300), 상기 함몰영역의 바닥면의 제2 산화막을 제거하는 단계(S400) 및 나노 와이어가 부유되도록, 상기 기판을 습식 식각하는 단계(S500)를 포함하는 마이크로 스케일 실리콘 구조물과 통합되는 실리콘 나노 와이어 제조방법에 관련된다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzLEKwjAQgOEuDqK-w4Gz0NoljiG9tIdNApcLdStF4iRaqO-PCOLs9C8f_7q4OO2T1UYSk2_BoXShARsYIvVkggevfRiIMQJ5wZa1YAMDSQeODIdodI8_HIXT54VxW6xu033Ju283xd6imO6Q5-eYl3m65kd-jWc-lpUqq7pS6qTr_9QbBVYyyg</recordid><startdate>20181211</startdate><enddate>20181211</enddate><creator>CHO, DONG IL</creator><creator>YOO, HYUNG JUNG</creator><creator>SHIN, JONG YOON</creator><creator>JANG, SEO HYEONG</creator><scope>EVB</scope></search><sort><creationdate>20181211</creationdate><title>MANUFACTURING METHOD FOR SILICON NANOWIRES INTEGRATED WITH MICROSCALE SILICON STRUCTURES</title><author>CHO, DONG IL ; YOO, HYUNG JUNG ; SHIN, JONG YOON ; JANG, SEO HYEONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20180131889A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHO, DONG IL</creatorcontrib><creatorcontrib>YOO, HYUNG JUNG</creatorcontrib><creatorcontrib>SHIN, JONG YOON</creatorcontrib><creatorcontrib>JANG, SEO HYEONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHO, DONG IL</au><au>YOO, HYUNG JUNG</au><au>SHIN, JONG YOON</au><au>JANG, SEO HYEONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURING METHOD FOR SILICON NANOWIRES INTEGRATED WITH MICROSCALE SILICON STRUCTURES</title><date>2018-12-11</date><risdate>2018</risdate><abstract>Embodiments of the present invention relate to a method for manufacturing a silicon nanowire integrated with a microscale silicon structure. The method comprises the steps of: (S100) forming a first oxide film on a substrate; (S200) etching the substrate to form a recessed region for separating a nanowire region and a microscale structure region using the first oxide film as a mask; (S300) forming a second oxide film on the etched substrate through a thermal oxidation process; (S400) removing the second oxide film on a bottom surface of the recessed; and (S500) performing wet etching on the substrate to float a nanowire. Therefore, the method may individually control a width and thickness of the nanowire.
실시예들은 기판 상에 제1 산화막을 형성하는 단계(S100), 제1 산화막을 마스크로 이용하여, 나노 와이어 영역과 마이크로 스케일 구조물 영역을 구분하는 함몰영역이 생성되도록 기판을 식각하는 단계(S200), 식각된 기판 상에 열산화 공정을 통해 제2 산화막을 형성하는 단계(S300), 상기 함몰영역의 바닥면의 제2 산화막을 제거하는 단계(S400) 및 나노 와이어가 부유되도록, 상기 기판을 습식 식각하는 단계(S500)를 포함하는 마이크로 스케일 실리콘 구조물과 통합되는 실리콘 나노 와이어 제조방법에 관련된다.</abstract><oa>free_for_read</oa></addata></record> |
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| title | MANUFACTURING METHOD FOR SILICON NANOWIRES INTEGRATED WITH MICROSCALE SILICON STRUCTURES |
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