TEST CIRCUIT OF SEMICONDUCTOR MEMORY
The present invention relates to a test circuit of a semiconductor memory, which can reduce a test time by quickly adjusting a voltage of a cell plate to a desired level. The test circuit of a semiconductor memory may comprise a plurality of first cell plates formed in a first memory block; a plural...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | The present invention relates to a test circuit of a semiconductor memory, which can reduce a test time by quickly adjusting a voltage of a cell plate to a desired level. The test circuit of a semiconductor memory may comprise a plurality of first cell plates formed in a first memory block; a plurality of second cell plates formed in a second memory block; and a switch configured to connect the plurality of first cell plates and the plurality of second cell plates according to a first control signal.
본 기술은 제 1 메모리 블록에 형성된 복수의 제 1 셀 플레이트; 제 2 메모리 블록에 형성된 복수의 제 2 셀 플레이트; 및 제 1 제어 신호에 따라 상기 복수의 제 1 셀 플레이트와 상기 복수의 제 2 셀 플레이트를 연결하도록 구성된 스위치를 포함할 수 있다. |
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