CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT

예시적인 자동 테스트 장비(ATE)는: DUT가 장착된 디바이스 인터페이스 보드(DIB); 상기 DUT로 신호를 전송하고 상기 DUT로부터 신호를 수신하는 시스템; 및 상기 DIB를 통해 상기 DUT에 전류를 제공하는 에너지 소스 유닛(ESU);을 포함하고, 상기 ESU는 전류를 공급하기 위한 전류 경로를 포함하고, 상기 전류 경로는 상기 전류 경로들의 결합된 인덕턴스를 제한하도록 구성된다. Example automatic test equipment (ATE) may include: a device interface board (D...

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Hauptverfasser: PRICE STEVEN C, WEIMER JACK E, BAENEN JEFFRY, HANNA DAVID R, SKIBINSKI SCOTT
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creator PRICE STEVEN C
WEIMER JACK E
BAENEN JEFFRY
HANNA DAVID R
SKIBINSKI SCOTT
description 예시적인 자동 테스트 장비(ATE)는: DUT가 장착된 디바이스 인터페이스 보드(DIB); 상기 DUT로 신호를 전송하고 상기 DUT로부터 신호를 수신하는 시스템; 및 상기 DIB를 통해 상기 DUT에 전류를 제공하는 에너지 소스 유닛(ESU);을 포함하고, 상기 ESU는 전류를 공급하기 위한 전류 경로를 포함하고, 상기 전류 경로는 상기 전류 경로들의 결합된 인덕턴스를 제한하도록 구성된다. Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20170029436A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20170029436A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20170029436A3</originalsourceid><addsrcrecordid>eNrjZLBz9vcLCfL38fH0c1cI9nT3c_RRCHAM8VDw9HMJdQ5x9HN2BTIVHEND_H0dQzydFUJcg0MUXANDPQN8Xf1CeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJvHeQkYGhuYGBkaWJsZmjMXGqABhRKy8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT</title><source>esp@cenet</source><creator>PRICE STEVEN C ; WEIMER JACK E ; BAENEN JEFFRY ; HANNA DAVID R ; SKIBINSKI SCOTT</creator><creatorcontrib>PRICE STEVEN C ; WEIMER JACK E ; BAENEN JEFFRY ; HANNA DAVID R ; SKIBINSKI SCOTT</creatorcontrib><description>예시적인 자동 테스트 장비(ATE)는: DUT가 장착된 디바이스 인터페이스 보드(DIB); 상기 DUT로 신호를 전송하고 상기 DUT로부터 신호를 수신하는 시스템; 및 상기 DIB를 통해 상기 DUT에 전류를 제공하는 에너지 소스 유닛(ESU);을 포함하고, 상기 ESU는 전류를 공급하기 위한 전류 경로를 포함하고, 상기 전류 경로는 상기 전류 경로들의 결합된 인덕턴스를 제한하도록 구성된다. Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.</description><language>eng ; kor</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170315&amp;DB=EPODOC&amp;CC=KR&amp;NR=20170029436A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170315&amp;DB=EPODOC&amp;CC=KR&amp;NR=20170029436A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PRICE STEVEN C</creatorcontrib><creatorcontrib>WEIMER JACK E</creatorcontrib><creatorcontrib>BAENEN JEFFRY</creatorcontrib><creatorcontrib>HANNA DAVID R</creatorcontrib><creatorcontrib>SKIBINSKI SCOTT</creatorcontrib><title>CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT</title><description>예시적인 자동 테스트 장비(ATE)는: DUT가 장착된 디바이스 인터페이스 보드(DIB); 상기 DUT로 신호를 전송하고 상기 DUT로부터 신호를 수신하는 시스템; 및 상기 DIB를 통해 상기 DUT에 전류를 제공하는 에너지 소스 유닛(ESU);을 포함하고, 상기 ESU는 전류를 공급하기 위한 전류 경로를 포함하고, 상기 전류 경로는 상기 전류 경로들의 결합된 인덕턴스를 제한하도록 구성된다. Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBz9vcLCfL38fH0c1cI9nT3c_RRCHAM8VDw9HMJdQ5x9HN2BTIVHEND_H0dQzydFUJcg0MUXANDPQN8Xf1CeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJvHeQkYGhuYGBkaWJsZmjMXGqABhRKy8</recordid><startdate>20170315</startdate><enddate>20170315</enddate><creator>PRICE STEVEN C</creator><creator>WEIMER JACK E</creator><creator>BAENEN JEFFRY</creator><creator>HANNA DAVID R</creator><creator>SKIBINSKI SCOTT</creator><scope>EVB</scope></search><sort><creationdate>20170315</creationdate><title>CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT</title><author>PRICE STEVEN C ; WEIMER JACK E ; BAENEN JEFFRY ; HANNA DAVID R ; SKIBINSKI SCOTT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20170029436A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2017</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>PRICE STEVEN C</creatorcontrib><creatorcontrib>WEIMER JACK E</creatorcontrib><creatorcontrib>BAENEN JEFFRY</creatorcontrib><creatorcontrib>HANNA DAVID R</creatorcontrib><creatorcontrib>SKIBINSKI SCOTT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PRICE STEVEN C</au><au>WEIMER JACK E</au><au>BAENEN JEFFRY</au><au>HANNA DAVID R</au><au>SKIBINSKI SCOTT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT</title><date>2017-03-15</date><risdate>2017</risdate><abstract>예시적인 자동 테스트 장비(ATE)는: DUT가 장착된 디바이스 인터페이스 보드(DIB); 상기 DUT로 신호를 전송하고 상기 DUT로부터 신호를 수신하는 시스템; 및 상기 DIB를 통해 상기 DUT에 전류를 제공하는 에너지 소스 유닛(ESU);을 포함하고, 상기 ESU는 전류를 공급하기 위한 전류 경로를 포함하고, 상기 전류 경로는 상기 전류 경로들의 결합된 인덕턴스를 제한하도록 구성된다. Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.</abstract><oa>free_for_read</oa></addata></record>
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subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT
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