Wafer Level Package
A wafer level package according to the technical idea of the present invention includes a substrate, a plurality of semiconductor chips mounted on the substrate, and a molding member formed on the substrate while touching the substrate and the plurality of semiconductor chips. The molding member com...
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| Format: | Patent |
| Sprache: | eng ; kor |
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| Zusammenfassung: | A wafer level package according to the technical idea of the present invention includes a substrate, a plurality of semiconductor chips mounted on the substrate, and a molding member formed on the substrate while touching the substrate and the plurality of semiconductor chips. The molding member comprises at least two parts with different thermal expansion coefficients. So, warpage can be easily controlled.
본 발명의 기술적 사상에 의한 웨이퍼 레벨 패키지는, 기판, 기판 상에 실장된 복수의 반도체 칩들, 그리고 기판 및 복수의 반도체 칩들과 접촉하면서 기판 상에 형성된 몰딩 부재를 포함하고, 몰딩 부재는 열 팽창 계수가 서로 다른 적어도 둘 이상의 부분으로 이루어진 것을 특징으로 한다. |
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