A method of forming fine pattern in semiconductor device

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the processes of: forming a mask pattern on a substrate where a layer to be etched is formed; forming a first sub trench by etching a part of the layer to be etched, exposed to a first defo...

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Hauptverfasser: JEON, KYUNG YUB, KIM, SUNG YEON, PARK, JIN YOUNG, KIM, KYO HYEOK, KIM, DONG CHAN, HAN, JE WOO, YOON, JUN HO, PARK, JAE HONG
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creator JEON, KYUNG YUB
KIM, SUNG YEON
PARK, JIN YOUNG
KIM, KYO HYEOK
KIM, DONG CHAN
HAN, JE WOO
YOON, JUN HO
PARK, JAE HONG
description A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the processes of: forming a mask pattern on a substrate where a layer to be etched is formed; forming a first sub trench by etching a part of the layer to be etched, exposed to a first deformed pattern formed on a side wall of the mask pattern through a first etching process; and forming a second sub trench by continuously etching the layer to be etched, which is exposed to a second deformed pattern formed on the side wall of the mask pattern and is exposed by the first sub trench, through a second etching process. An outer side wall of the first deformed pattern has a first angle with respect to an upper plane of the substrate, and an outer side wall of the second deformed pattern has a second angle different from the first angle with respect to the upper plane of the substrate. The objective of the present invention is to provide the semiconductor device having the fine pattern with a good profile. 본 발명의 실시예에 따른 반도체 소자의 제조 방법은 식각 대상막이 형성된 기판 상에 마스크 패턴을 형성하는 것, 제 1 식각 공정에 의해 상기 마스크 패턴의 측벽에 형성된 제 1 변형 패턴에 노출된 식각 대상막의 일부분을 식각하여 제 1 서브 트렌치를 형성하는 것, 및 제 2 식각 공정에 의해, 상기 마스크 패턴의 상기 측벽에 형성된 제 2 변형패턴에 노출되고 상기 제 1 서브 트렌치에 의해 노출된 상기 식각 대상막을 연속적으로 식각하여 제 2 서브 트렌치를 형성하는 것을 포함하되, 상기 제 1 변형패턴의 외측벽은 상기 기판의 상부면에 대해 제 1 각도를 갖고, 상기 제 2 변형패턴의 외측벽은 상기 기판의 상부면에 대해 상기 제 1 각도와 다른 제 2 각도를 가질 수 있다.
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An outer side wall of the first deformed pattern has a first angle with respect to an upper plane of the substrate, and an outer side wall of the second deformed pattern has a second angle different from the first angle with respect to the upper plane of the substrate. The objective of the present invention is to provide the semiconductor device having the fine pattern with a good profile. 본 발명의 실시예에 따른 반도체 소자의 제조 방법은 식각 대상막이 형성된 기판 상에 마스크 패턴을 형성하는 것, 제 1 식각 공정에 의해 상기 마스크 패턴의 측벽에 형성된 제 1 변형 패턴에 노출된 식각 대상막의 일부분을 식각하여 제 1 서브 트렌치를 형성하는 것, 및 제 2 식각 공정에 의해, 상기 마스크 패턴의 상기 측벽에 형성된 제 2 변형패턴에 노출되고 상기 제 1 서브 트렌치에 의해 노출된 상기 식각 대상막을 연속적으로 식각하여 제 2 서브 트렌치를 형성하는 것을 포함하되, 상기 제 1 변형패턴의 외측벽은 상기 기판의 상부면에 대해 제 1 각도를 갖고, 상기 제 2 변형패턴의 외측벽은 상기 기판의 상부면에 대해 상기 제 1 각도와 다른 제 2 각도를 가질 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20161013&amp;DB=EPODOC&amp;CC=KR&amp;NR=20160119329A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20161013&amp;DB=EPODOC&amp;CC=KR&amp;NR=20160119329A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JEON, KYUNG YUB</creatorcontrib><creatorcontrib>KIM, SUNG YEON</creatorcontrib><creatorcontrib>PARK, JIN YOUNG</creatorcontrib><creatorcontrib>KIM, KYO HYEOK</creatorcontrib><creatorcontrib>KIM, DONG CHAN</creatorcontrib><creatorcontrib>HAN, JE WOO</creatorcontrib><creatorcontrib>YOON, JUN HO</creatorcontrib><creatorcontrib>PARK, JAE HONG</creatorcontrib><title>A method of forming fine pattern in semiconductor device</title><description>A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the processes of: forming a mask pattern on a substrate where a layer to be etched is formed; forming a first sub trench by etching a part of the layer to be etched, exposed to a first deformed pattern formed on a side wall of the mask pattern through a first etching process; and forming a second sub trench by continuously etching the layer to be etched, which is exposed to a second deformed pattern formed on the side wall of the mask pattern and is exposed by the first sub trench, through a second etching process. An outer side wall of the first deformed pattern has a first angle with respect to an upper plane of the substrate, and an outer side wall of the second deformed pattern has a second angle different from the first angle with respect to the upper plane of the substrate. The objective of the present invention is to provide the semiconductor device having the fine pattern with a good profile. 본 발명의 실시예에 따른 반도체 소자의 제조 방법은 식각 대상막이 형성된 기판 상에 마스크 패턴을 형성하는 것, 제 1 식각 공정에 의해 상기 마스크 패턴의 측벽에 형성된 제 1 변형 패턴에 노출된 식각 대상막의 일부분을 식각하여 제 1 서브 트렌치를 형성하는 것, 및 제 2 식각 공정에 의해, 상기 마스크 패턴의 상기 측벽에 형성된 제 2 변형패턴에 노출되고 상기 제 1 서브 트렌치에 의해 노출된 상기 식각 대상막을 연속적으로 식각하여 제 2 서브 트렌치를 형성하는 것을 포함하되, 상기 제 1 변형패턴의 외측벽은 상기 기판의 상부면에 대해 제 1 각도를 갖고, 상기 제 2 변형패턴의 외측벽은 상기 기판의 상부면에 대해 상기 제 1 각도와 다른 제 2 각도를 가질 수 있다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBwVMhNLcnIT1HIT1NIyy_KzcxLV0jLzEtVKEgsKUktylPIzFMoTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGhmYGhoaWxkaWjsbEqQIAlkYu7g</recordid><startdate>20161013</startdate><enddate>20161013</enddate><creator>JEON, KYUNG YUB</creator><creator>KIM, SUNG YEON</creator><creator>PARK, JIN YOUNG</creator><creator>KIM, KYO HYEOK</creator><creator>KIM, DONG CHAN</creator><creator>HAN, JE WOO</creator><creator>YOON, JUN HO</creator><creator>PARK, JAE HONG</creator><scope>EVB</scope></search><sort><creationdate>20161013</creationdate><title>A method of forming fine pattern in semiconductor device</title><author>JEON, KYUNG YUB ; KIM, SUNG YEON ; PARK, JIN YOUNG ; KIM, KYO HYEOK ; KIM, DONG CHAN ; HAN, JE WOO ; YOON, JUN HO ; PARK, JAE HONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20160119329A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JEON, KYUNG YUB</creatorcontrib><creatorcontrib>KIM, SUNG YEON</creatorcontrib><creatorcontrib>PARK, JIN YOUNG</creatorcontrib><creatorcontrib>KIM, KYO HYEOK</creatorcontrib><creatorcontrib>KIM, DONG CHAN</creatorcontrib><creatorcontrib>HAN, JE WOO</creatorcontrib><creatorcontrib>YOON, JUN HO</creatorcontrib><creatorcontrib>PARK, JAE HONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEON, KYUNG YUB</au><au>KIM, SUNG YEON</au><au>PARK, JIN YOUNG</au><au>KIM, KYO HYEOK</au><au>KIM, DONG CHAN</au><au>HAN, JE WOO</au><au>YOON, JUN HO</au><au>PARK, JAE HONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A method of forming fine pattern in semiconductor device</title><date>2016-10-13</date><risdate>2016</risdate><abstract>A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the processes of: forming a mask pattern on a substrate where a layer to be etched is formed; forming a first sub trench by etching a part of the layer to be etched, exposed to a first deformed pattern formed on a side wall of the mask pattern through a first etching process; and forming a second sub trench by continuously etching the layer to be etched, which is exposed to a second deformed pattern formed on the side wall of the mask pattern and is exposed by the first sub trench, through a second etching process. An outer side wall of the first deformed pattern has a first angle with respect to an upper plane of the substrate, and an outer side wall of the second deformed pattern has a second angle different from the first angle with respect to the upper plane of the substrate. The objective of the present invention is to provide the semiconductor device having the fine pattern with a good profile. 본 발명의 실시예에 따른 반도체 소자의 제조 방법은 식각 대상막이 형성된 기판 상에 마스크 패턴을 형성하는 것, 제 1 식각 공정에 의해 상기 마스크 패턴의 측벽에 형성된 제 1 변형 패턴에 노출된 식각 대상막의 일부분을 식각하여 제 1 서브 트렌치를 형성하는 것, 및 제 2 식각 공정에 의해, 상기 마스크 패턴의 상기 측벽에 형성된 제 2 변형패턴에 노출되고 상기 제 1 서브 트렌치에 의해 노출된 상기 식각 대상막을 연속적으로 식각하여 제 2 서브 트렌치를 형성하는 것을 포함하되, 상기 제 1 변형패턴의 외측벽은 상기 기판의 상부면에 대해 제 1 각도를 갖고, 상기 제 2 변형패턴의 외측벽은 상기 기판의 상부면에 대해 상기 제 1 각도와 다른 제 2 각도를 가질 수 있다.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title A method of forming fine pattern in semiconductor device
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