SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

The present invention relates to a semiconductor package, and a method for manufacturing the same. According to the present invention, the semiconductor package comprises: a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer for exposing an upper surface...

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description The present invention relates to a semiconductor package, and a method for manufacturing the same. According to the present invention, the semiconductor package comprises: a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer for exposing an upper surface of the lower semiconductor chip; bumps separated from the lower semiconductor chip on the lower substrate; a lead frame arranged on the lower semiconductor chip and the bumps, and electrically connected to the bumps; and an upper package arranged on the lead frame, and electrically connected to the lead frame. 본 발명은 반도체 패키지 및 그 제조 방법을 제공한다. 본 발명에 따른 반도체 패키지는 하부 기판, 하부 반도체칩, 그리고 상기 하부 반도체칩의 상면을 노출시키는 하부 몰딩막을 포함하는 하부 패키지; 상기 하부 기판 상에서 상기 하부 반도체칩과 이격된 범프들; 상기 하부 반도체칩 및 상기 범프들 상에 배치되고, 상기 범프들과 전기적으로 연결되는 리드 프레임; 및 상기 리드 프레임 상에 배치되고, 상기 리드 프레임과 전기적으로 연결되는 상부 패키지를 포함할 수 있다.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20150142140A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20150142140A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20150142140A3</originalsourceid><addsrcrecordid>eNrjZLAKdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkN8vRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgaGpgaGJkaGJgaOxsSpAgBBDSmU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME</title><source>esp@cenet</source><creator>IM, YUN HYEOK</creator><creatorcontrib>IM, YUN HYEOK</creatorcontrib><description>The present invention relates to a semiconductor package, and a method for manufacturing the same. According to the present invention, the semiconductor package comprises: a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer for exposing an upper surface of the lower semiconductor chip; bumps separated from the lower semiconductor chip on the lower substrate; a lead frame arranged on the lower semiconductor chip and the bumps, and electrically connected to the bumps; and an upper package arranged on the lead frame, and electrically connected to the lead frame. 본 발명은 반도체 패키지 및 그 제조 방법을 제공한다. 본 발명에 따른 반도체 패키지는 하부 기판, 하부 반도체칩, 그리고 상기 하부 반도체칩의 상면을 노출시키는 하부 몰딩막을 포함하는 하부 패키지; 상기 하부 기판 상에서 상기 하부 반도체칩과 이격된 범프들; 상기 하부 반도체칩 및 상기 범프들 상에 배치되고, 상기 범프들과 전기적으로 연결되는 리드 프레임; 및 상기 리드 프레임 상에 배치되고, 상기 리드 프레임과 전기적으로 연결되는 상부 패키지를 포함할 수 있다.</description><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151222&amp;DB=EPODOC&amp;CC=KR&amp;NR=20150142140A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151222&amp;DB=EPODOC&amp;CC=KR&amp;NR=20150142140A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>IM, YUN HYEOK</creatorcontrib><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME</title><description>The present invention relates to a semiconductor package, and a method for manufacturing the same. According to the present invention, the semiconductor package comprises: a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer for exposing an upper surface of the lower semiconductor chip; bumps separated from the lower semiconductor chip on the lower substrate; a lead frame arranged on the lower semiconductor chip and the bumps, and electrically connected to the bumps; and an upper package arranged on the lead frame, and electrically connected to the lead frame. 본 발명은 반도체 패키지 및 그 제조 방법을 제공한다. 본 발명에 따른 반도체 패키지는 하부 기판, 하부 반도체칩, 그리고 상기 하부 반도체칩의 상면을 노출시키는 하부 몰딩막을 포함하는 하부 패키지; 상기 하부 기판 상에서 상기 하부 반도체칩과 이격된 범프들; 상기 하부 반도체칩 및 상기 범프들 상에 배치되고, 상기 범프들과 전기적으로 연결되는 리드 프레임; 및 상기 리드 프레임 상에 배치되고, 상기 리드 프레임과 전기적으로 연결되는 상부 패키지를 포함할 수 있다.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfQLdXN0DgkN8vRzVwjxcFUIdvR15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgaGpgaGJkaGJgaOxsSpAgBBDSmU</recordid><startdate>20151222</startdate><enddate>20151222</enddate><creator>IM, YUN HYEOK</creator><scope>EVB</scope></search><sort><creationdate>20151222</creationdate><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME</title><author>IM, YUN HYEOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20150142140A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>IM, YUN HYEOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>IM, YUN HYEOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME</title><date>2015-12-22</date><risdate>2015</risdate><abstract>The present invention relates to a semiconductor package, and a method for manufacturing the same. According to the present invention, the semiconductor package comprises: a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer for exposing an upper surface of the lower semiconductor chip; bumps separated from the lower semiconductor chip on the lower substrate; a lead frame arranged on the lower semiconductor chip and the bumps, and electrically connected to the bumps; and an upper package arranged on the lead frame, and electrically connected to the lead frame. 본 발명은 반도체 패키지 및 그 제조 방법을 제공한다. 본 발명에 따른 반도체 패키지는 하부 기판, 하부 반도체칩, 그리고 상기 하부 반도체칩의 상면을 노출시키는 하부 몰딩막을 포함하는 하부 패키지; 상기 하부 기판 상에서 상기 하부 반도체칩과 이격된 범프들; 상기 하부 반도체칩 및 상기 범프들 상에 배치되고, 상기 범프들과 전기적으로 연결되는 리드 프레임; 및 상기 리드 프레임 상에 배치되고, 상기 리드 프레임과 전기적으로 연결되는 상부 패키지를 포함할 수 있다.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T12%3A19%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=IM,%20YUN%20HYEOK&rft.date=2015-12-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20150142140A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true