DEVICE EMBEDDED PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Provided is a package substrate which includes: a core layer which includes a core top side and a core bottom side which includes a board connection region; and a buildup layer which has a stack structure by alternately stacking a plurality of wire layers and a plurality of insulation layers on the...
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| creator | MYUNG, BOK SIK KIM, CHUL WOO LEE, SEUNG HWAN NA, KYUNG TAE |
| description | Provided is a package substrate which includes: a core layer which includes a core top side and a core bottom side which includes a board connection region; and a buildup layer which has a stack structure by alternately stacking a plurality of wire layers and a plurality of insulation layers on the core top side and includes a chip mounting region on the surface thereof. The core layer includes recess sidewalls which are upwardly extended from the core bottom side; at least one cavity which is limited by the recessed surface which is located to be higher than the core top side or with the same level as the core top side; at least one device which is mounted in at least one cavity; and through electrodes which electrically connect the core top side and the core bottom side. |
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| language | eng ; kor |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | DEVICE EMBEDDED PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME |
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