METHOD FOR CIRCUIT SIMULATION

PURPOSE: A circuit simulation method is provided to use a net list and a waveform with a digital value, thereby increasing error inspection speed for a circuit and performing various error inspections. CONSTITUTION: A net list is generated for a designed circuit, and the operation of the circuit is...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PARK, SANG HO, YUN, YEO IL, MIN, SEONG UK
Format: Patent
Sprache:eng ; kor
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator PARK, SANG HO
YUN, YEO IL
MIN, SEONG UK
description PURPOSE: A circuit simulation method is provided to use a net list and a waveform with a digital value, thereby increasing error inspection speed for a circuit and performing various error inspections. CONSTITUTION: A net list is generated for a designed circuit, and the operation of the circuit is simulated by using the generated net list(S300). Errors in the circuit are inspected by using the net list and the waveform which is generated in a simulation step(S400). Errors in the circuit are inspected by using the inspection control information and the waveform. [Reference numerals] (AA) Start; (BB) End; (S100) Circuit design; (S200) Net list generation; (S300) Circuit simulation; (S400) Circuit error inspection using a waveform generated in net list and simulation;
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20130035555A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20130035555A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20130035555A3</originalsourceid><addsrcrecordid>eNrjZJD1dQ3x8HdRcPMPUnD2DHIO9QxRCPb0DfVxDPH09-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGhsYGBsamQOBoTJwqABnSIfo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR CIRCUIT SIMULATION</title><source>esp@cenet</source><creator>PARK, SANG HO ; YUN, YEO IL ; MIN, SEONG UK</creator><creatorcontrib>PARK, SANG HO ; YUN, YEO IL ; MIN, SEONG UK</creatorcontrib><description>PURPOSE: A circuit simulation method is provided to use a net list and a waveform with a digital value, thereby increasing error inspection speed for a circuit and performing various error inspections. CONSTITUTION: A net list is generated for a designed circuit, and the operation of the circuit is simulated by using the generated net list(S300). Errors in the circuit are inspected by using the net list and the waveform which is generated in a simulation step(S400). Errors in the circuit are inspected by using the inspection control information and the waveform. [Reference numerals] (AA) Start; (BB) End; (S100) Circuit design; (S200) Net list generation; (S300) Circuit simulation; (S400) Circuit error inspection using a waveform generated in net list and simulation;</description><language>eng ; kor</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130409&amp;DB=EPODOC&amp;CC=KR&amp;NR=20130035555A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130409&amp;DB=EPODOC&amp;CC=KR&amp;NR=20130035555A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARK, SANG HO</creatorcontrib><creatorcontrib>YUN, YEO IL</creatorcontrib><creatorcontrib>MIN, SEONG UK</creatorcontrib><title>METHOD FOR CIRCUIT SIMULATION</title><description>PURPOSE: A circuit simulation method is provided to use a net list and a waveform with a digital value, thereby increasing error inspection speed for a circuit and performing various error inspections. CONSTITUTION: A net list is generated for a designed circuit, and the operation of the circuit is simulated by using the generated net list(S300). Errors in the circuit are inspected by using the net list and the waveform which is generated in a simulation step(S400). Errors in the circuit are inspected by using the inspection control information and the waveform. [Reference numerals] (AA) Start; (BB) End; (S100) Circuit design; (S200) Net list generation; (S300) Circuit simulation; (S400) Circuit error inspection using a waveform generated in net list and simulation;</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD1dQ3x8HdRcPMPUnD2DHIO9QxRCPb0DfVxDPH09-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQUYGhsYGBsamQOBoTJwqABnSIfo</recordid><startdate>20130409</startdate><enddate>20130409</enddate><creator>PARK, SANG HO</creator><creator>YUN, YEO IL</creator><creator>MIN, SEONG UK</creator><scope>EVB</scope></search><sort><creationdate>20130409</creationdate><title>METHOD FOR CIRCUIT SIMULATION</title><author>PARK, SANG HO ; YUN, YEO IL ; MIN, SEONG UK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20130035555A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>PARK, SANG HO</creatorcontrib><creatorcontrib>YUN, YEO IL</creatorcontrib><creatorcontrib>MIN, SEONG UK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARK, SANG HO</au><au>YUN, YEO IL</au><au>MIN, SEONG UK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR CIRCUIT SIMULATION</title><date>2013-04-09</date><risdate>2013</risdate><abstract>PURPOSE: A circuit simulation method is provided to use a net list and a waveform with a digital value, thereby increasing error inspection speed for a circuit and performing various error inspections. CONSTITUTION: A net list is generated for a designed circuit, and the operation of the circuit is simulated by using the generated net list(S300). Errors in the circuit are inspected by using the net list and the waveform which is generated in a simulation step(S400). Errors in the circuit are inspected by using the inspection control information and the waveform. [Reference numerals] (AA) Start; (BB) End; (S100) Circuit design; (S200) Net list generation; (S300) Circuit simulation; (S400) Circuit error inspection using a waveform generated in net list and simulation;</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; kor
recordid cdi_epo_espacenet_KR20130035555A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title METHOD FOR CIRCUIT SIMULATION
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T06%3A23%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PARK,%20SANG%20HO&rft.date=2013-04-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20130035555A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true