MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL

A memory having at least one memory array block (10), the at least one memory array block (10) comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers (28, 29) coupled to the at least one memory array block (10). The memory further com...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHILDS LAWRENCE F, LU OLGA R, JETTON MARK W, STARNES GLENN E
Format:	Patent
Sprache:	eng ; kor
Schlagworte:	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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