MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL

A memory having at least one memory array block (10), the at least one memory array block (10) comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers (28, 29) coupled to the at least one memory array block (10). The memory further comprises at least one dummy bitline (40, 41), wherein the at least one dummy bitline (40, 41) comprises M dummy bitcells (42, 43), wherein M is equal to N. The memory further comprises a timing circuit (20) coupled to the at least one dummy bitline (40, 41), wherein the timing circuit (20) comprises at least one stack of pull-down transistors (60, 61) coupled to a sense circuit (70) for generating a latch control output signal (104) used for timing control of memory accesses. Timing control may include generating a sense trigger signal (44) to enable the plurality of sense amplifiers (28, 29) for read operations and/or generating a local reset signal (100) for terminating memory accesses, such as disabling the plurality of write drivers (26, 27) for write operations.