METHOD FOR FORMING CU LINE OF SEMICONDUCTOR DEVICE
A method for forming a copper wiring of a semiconductor device is provided to reduce a manufacturing cost by removing fundamentally defects generated in a chemical mechanical polishing process. A first etch-stop layer, a first interlayer dielectric, a second etch-stop layer, and a second interlayer...
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| creator | KIM, GWAN SU |
| description | A method for forming a copper wiring of a semiconductor device is provided to reduce a manufacturing cost by removing fundamentally defects generated in a chemical mechanical polishing process. A first etch-stop layer, a first interlayer dielectric, a second etch-stop layer, and a second interlayer dielectric are stacked on an upper part of a semiconductor substrate(100). A via hole and a trench are formed by patterning the first etch-stop layer(110), the first interlayer dielectric(120), the second etch-stop layer, and the second interlayer dielectric. The via hole and the trench are filled with copper. The copper is deposited on an upper part of the second interlayer dielectric in order to form a copper layer. The copper layer is etched to expose an inner surface and an upper surface of the second interlayer dielectric connected with the trench. A copper wiring is formed by etching the second interlayer dielectric. |
| format | Patent |
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A first etch-stop layer, a first interlayer dielectric, a second etch-stop layer, and a second interlayer dielectric are stacked on an upper part of a semiconductor substrate(100). A via hole and a trench are formed by patterning the first etch-stop layer(110), the first interlayer dielectric(120), the second etch-stop layer, and the second interlayer dielectric. The via hole and the trench are filled with copper. The copper is deposited on an upper part of the second interlayer dielectric in order to form a copper layer. The copper layer is etched to expose an inner surface and an upper surface of the second interlayer dielectric connected with the trench. A copper wiring is formed by etching the second interlayer dielectric.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090623&DB=EPODOC&CC=KR&NR=20090065969A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090623&DB=EPODOC&CC=KR&NR=20090065969A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, GWAN SU</creatorcontrib><title>METHOD FOR FORMING CU LINE OF SEMICONDUCTOR DEVICE</title><description>A method for forming a copper wiring of a semiconductor device is provided to reduce a manufacturing cost by removing fundamentally defects generated in a chemical mechanical polishing process. A first etch-stop layer, a first interlayer dielectric, a second etch-stop layer, and a second interlayer dielectric are stacked on an upper part of a semiconductor substrate(100). A via hole and a trench are formed by patterning the first etch-stop layer(110), the first interlayer dielectric(120), the second etch-stop layer, and the second interlayer dielectric. The via hole and the trench are filled with copper. The copper is deposited on an upper part of the second interlayer dielectric in order to form a copper layer. The copper layer is etched to expose an inner surface and an upper surface of the second interlayer dielectric connected with the trench. A copper wiring is formed by etching the second interlayer dielectric.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDydQ3x8HdRcPMPAmFfTz93BedQBR9PP1cFfzeFYFdfT2d_P5dQ5xCgAhfXME9nVx4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEu8dZGRgYGlgYGZqaWbpaEycKgD4cSeP</recordid><startdate>20090623</startdate><enddate>20090623</enddate><creator>KIM, GWAN SU</creator><scope>EVB</scope></search><sort><creationdate>20090623</creationdate><title>METHOD FOR FORMING CU LINE OF SEMICONDUCTOR DEVICE</title><author>KIM, GWAN SU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20090065969A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, GWAN SU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, GWAN SU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR FORMING CU LINE OF SEMICONDUCTOR DEVICE</title><date>2009-06-23</date><risdate>2009</risdate><abstract>A method for forming a copper wiring of a semiconductor device is provided to reduce a manufacturing cost by removing fundamentally defects generated in a chemical mechanical polishing process. A first etch-stop layer, a first interlayer dielectric, a second etch-stop layer, and a second interlayer dielectric are stacked on an upper part of a semiconductor substrate(100). A via hole and a trench are formed by patterning the first etch-stop layer(110), the first interlayer dielectric(120), the second etch-stop layer, and the second interlayer dielectric. The via hole and the trench are filled with copper. The copper is deposited on an upper part of the second interlayer dielectric in order to form a copper layer. The copper layer is etched to expose an inner surface and an upper surface of the second interlayer dielectric connected with the trench. A copper wiring is formed by etching the second interlayer dielectric.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD FOR FORMING CU LINE OF SEMICONDUCTOR DEVICE |
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