METHOD AND APPARATUS FOR TESTING DATA STEERING LOGIC FOR DATA STORAGE HAVING INDEPENDENTLY ADDRESSABLE SUBUNITS

Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PATEL SANJAY B, MAMILETI LAKSHMIKANT, MUMFORD CLINT WAYNE, KRISHNAMURTHY ANAND
Format: Patent
Sprache:eng
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