METHOD FOR PLANARIZATION OF DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE
A method for planarizing a dielectric of a semiconductor device is provided to prevent an upper surface of a gate electrode from being exposed to the outside by removing a step section of an interlayer dielectric on an upper portion of the gate electrode. A first dielectric is formed on an upper por...
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| creator | SONG, PIL GEUN KIM, HYUN JOO |
| description | A method for planarizing a dielectric of a semiconductor device is provided to prevent an upper surface of a gate electrode from being exposed to the outside by removing a step section of an interlayer dielectric on an upper portion of the gate electrode. A first dielectric is formed on an upper portion of a substrate(110) where a gate electrode(117B) is formed. A polish stop layer(121) is formed along an upper surface of the first dielectric including a step section of the first dielectric. The step section is generated when the first dielectric is formed. A second dielectric is formed along a step of an upper surface of the polish stop layer. The second dielectric and the polish stop layer are polished such that the polish stop layer remains in the step section. A first wet etching process is performed to etch the first dielectric so that the step section is removed. A second wet etching process is performed to remove the polish stop layer remaining on the first dielectric. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20080089090A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20080089090A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20080089090A3</originalsourceid><addsrcrecordid>eNrjZHDxdQ3x8HdRcPMPUgjwcfRzDPKMcgzx9PdT8HdTcPF09XF1DgnydFbwcYx0DVLw9FMIdvX1dPb3cwl1DgFqcXEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgYGFkBkaWBp4GhMnCoABI4sow</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR PLANARIZATION OF DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>SONG, PIL GEUN ; KIM, HYUN JOO</creator><creatorcontrib>SONG, PIL GEUN ; KIM, HYUN JOO</creatorcontrib><description>A method for planarizing a dielectric of a semiconductor device is provided to prevent an upper surface of a gate electrode from being exposed to the outside by removing a step section of an interlayer dielectric on an upper portion of the gate electrode. A first dielectric is formed on an upper portion of a substrate(110) where a gate electrode(117B) is formed. A polish stop layer(121) is formed along an upper surface of the first dielectric including a step section of the first dielectric. The step section is generated when the first dielectric is formed. A second dielectric is formed along a step of an upper surface of the polish stop layer. The second dielectric and the polish stop layer are polished such that the polish stop layer remains in the step section. A first wet etching process is performed to etch the first dielectric so that the step section is removed. A second wet etching process is performed to remove the polish stop layer remaining on the first dielectric.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081006&DB=EPODOC&CC=KR&NR=20080089090A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081006&DB=EPODOC&CC=KR&NR=20080089090A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SONG, PIL GEUN</creatorcontrib><creatorcontrib>KIM, HYUN JOO</creatorcontrib><title>METHOD FOR PLANARIZATION OF DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE</title><description>A method for planarizing a dielectric of a semiconductor device is provided to prevent an upper surface of a gate electrode from being exposed to the outside by removing a step section of an interlayer dielectric on an upper portion of the gate electrode. A first dielectric is formed on an upper portion of a substrate(110) where a gate electrode(117B) is formed. A polish stop layer(121) is formed along an upper surface of the first dielectric including a step section of the first dielectric. The step section is generated when the first dielectric is formed. A second dielectric is formed along a step of an upper surface of the polish stop layer. The second dielectric and the polish stop layer are polished such that the polish stop layer remains in the step section. A first wet etching process is performed to etch the first dielectric so that the step section is removed. A second wet etching process is performed to remove the polish stop layer remaining on the first dielectric.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDxdQ3x8HdRcPMPUgjwcfRzDPKMcgzx9PdT8HdTcPF09XF1DgnydFbwcYx0DVLw9FMIdvX1dPb3cwl1DgFqcXEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgYGFkBkaWBp4GhMnCoABI4sow</recordid><startdate>20081006</startdate><enddate>20081006</enddate><creator>SONG, PIL GEUN</creator><creator>KIM, HYUN JOO</creator><scope>EVB</scope></search><sort><creationdate>20081006</creationdate><title>METHOD FOR PLANARIZATION OF DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE</title><author>SONG, PIL GEUN ; KIM, HYUN JOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20080089090A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SONG, PIL GEUN</creatorcontrib><creatorcontrib>KIM, HYUN JOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SONG, PIL GEUN</au><au>KIM, HYUN JOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR PLANARIZATION OF DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE</title><date>2008-10-06</date><risdate>2008</risdate><abstract>A method for planarizing a dielectric of a semiconductor device is provided to prevent an upper surface of a gate electrode from being exposed to the outside by removing a step section of an interlayer dielectric on an upper portion of the gate electrode. A first dielectric is formed on an upper portion of a substrate(110) where a gate electrode(117B) is formed. A polish stop layer(121) is formed along an upper surface of the first dielectric including a step section of the first dielectric. The step section is generated when the first dielectric is formed. A second dielectric is formed along a step of an upper surface of the polish stop layer. The second dielectric and the polish stop layer are polished such that the polish stop layer remains in the step section. A first wet etching process is performed to etch the first dielectric so that the step section is removed. A second wet etching process is performed to remove the polish stop layer remaining on the first dielectric.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD FOR PLANARIZATION OF DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE |
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