METHOD OF FABRICATING SEMICONDUCTOR DEVICE

A method of fabricating a semiconductor device is provided to improve the reliability of a transistor, without deterioration of performance, by forming a thin stress liner layer and a thick stress liner layer. A transistor comprising a gate structure and a conductive region(208) is formed on a subst...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PARK, JAE EON, YANG, DAE WON, BAIOCCO CHRISTOPHER VINCENT, NAIR DELEEP R, CHEN XIANGDONG, KIM, JUN JUNG
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator PARK, JAE EON
YANG, DAE WON
BAIOCCO CHRISTOPHER VINCENT
NAIR DELEEP R
CHEN XIANGDONG
KIM, JUN JUNG
description A method of fabricating a semiconductor device is provided to improve the reliability of a transistor, without deterioration of performance, by forming a thin stress liner layer and a thick stress liner layer. A transistor comprising a gate structure and a conductive region(208) is formed on a substrate(200), in which the gate structure is patterned, and a spacer(206) is formed on a side of the gate structure. Conductive regions are formed within the substrate on both sides of the gate structure. The transistor is applied by a first plasma having a first power level to form a first stress layer(210) on the transistor. The transistor is applied by a second plasma having a second power level to from a second stress layer(212) on the first stress layer, in which the second power level is higher than the first power level.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20080060142A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20080060142A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20080060142A3</originalsourceid><addsrcrecordid>eNrjZNDydQ3x8HdR8HdTcHN0CvJ0dgzx9HNXCHb19XT293MJdQ7xD1JwcQ3zdHblYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kFGBgYWBgZmBoYmRo7GxKkCANUhJVo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF FABRICATING SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>PARK, JAE EON ; YANG, DAE WON ; BAIOCCO CHRISTOPHER VINCENT ; NAIR DELEEP R ; CHEN XIANGDONG ; KIM, JUN JUNG</creator><creatorcontrib>PARK, JAE EON ; YANG, DAE WON ; BAIOCCO CHRISTOPHER VINCENT ; NAIR DELEEP R ; CHEN XIANGDONG ; KIM, JUN JUNG</creatorcontrib><description>A method of fabricating a semiconductor device is provided to improve the reliability of a transistor, without deterioration of performance, by forming a thin stress liner layer and a thick stress liner layer. A transistor comprising a gate structure and a conductive region(208) is formed on a substrate(200), in which the gate structure is patterned, and a spacer(206) is formed on a side of the gate structure. Conductive regions are formed within the substrate on both sides of the gate structure. The transistor is applied by a first plasma having a first power level to form a first stress layer(210) on the transistor. The transistor is applied by a second plasma having a second power level to from a second stress layer(212) on the first stress layer, in which the second power level is higher than the first power level.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080701&amp;DB=EPODOC&amp;CC=KR&amp;NR=20080060142A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080701&amp;DB=EPODOC&amp;CC=KR&amp;NR=20080060142A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARK, JAE EON</creatorcontrib><creatorcontrib>YANG, DAE WON</creatorcontrib><creatorcontrib>BAIOCCO CHRISTOPHER VINCENT</creatorcontrib><creatorcontrib>NAIR DELEEP R</creatorcontrib><creatorcontrib>CHEN XIANGDONG</creatorcontrib><creatorcontrib>KIM, JUN JUNG</creatorcontrib><title>METHOD OF FABRICATING SEMICONDUCTOR DEVICE</title><description>A method of fabricating a semiconductor device is provided to improve the reliability of a transistor, without deterioration of performance, by forming a thin stress liner layer and a thick stress liner layer. A transistor comprising a gate structure and a conductive region(208) is formed on a substrate(200), in which the gate structure is patterned, and a spacer(206) is formed on a side of the gate structure. Conductive regions are formed within the substrate on both sides of the gate structure. The transistor is applied by a first plasma having a first power level to form a first stress layer(210) on the transistor. The transistor is applied by a second plasma having a second power level to from a second stress layer(212) on the first stress layer, in which the second power level is higher than the first power level.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDydQ3x8HdR8HdTcHN0CvJ0dgzx9HNXCHb19XT293MJdQ7xD1JwcQ3zdHblYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXx3kFGBgYWBgZmBoYmRo7GxKkCANUhJVo</recordid><startdate>20080701</startdate><enddate>20080701</enddate><creator>PARK, JAE EON</creator><creator>YANG, DAE WON</creator><creator>BAIOCCO CHRISTOPHER VINCENT</creator><creator>NAIR DELEEP R</creator><creator>CHEN XIANGDONG</creator><creator>KIM, JUN JUNG</creator><scope>EVB</scope></search><sort><creationdate>20080701</creationdate><title>METHOD OF FABRICATING SEMICONDUCTOR DEVICE</title><author>PARK, JAE EON ; YANG, DAE WON ; BAIOCCO CHRISTOPHER VINCENT ; NAIR DELEEP R ; CHEN XIANGDONG ; KIM, JUN JUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20080060142A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PARK, JAE EON</creatorcontrib><creatorcontrib>YANG, DAE WON</creatorcontrib><creatorcontrib>BAIOCCO CHRISTOPHER VINCENT</creatorcontrib><creatorcontrib>NAIR DELEEP R</creatorcontrib><creatorcontrib>CHEN XIANGDONG</creatorcontrib><creatorcontrib>KIM, JUN JUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARK, JAE EON</au><au>YANG, DAE WON</au><au>BAIOCCO CHRISTOPHER VINCENT</au><au>NAIR DELEEP R</au><au>CHEN XIANGDONG</au><au>KIM, JUN JUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF FABRICATING SEMICONDUCTOR DEVICE</title><date>2008-07-01</date><risdate>2008</risdate><abstract>A method of fabricating a semiconductor device is provided to improve the reliability of a transistor, without deterioration of performance, by forming a thin stress liner layer and a thick stress liner layer. A transistor comprising a gate structure and a conductive region(208) is formed on a substrate(200), in which the gate structure is patterned, and a spacer(206) is formed on a side of the gate structure. Conductive regions are formed within the substrate on both sides of the gate structure. The transistor is applied by a first plasma having a first power level to form a first stress layer(210) on the transistor. The transistor is applied by a second plasma having a second power level to from a second stress layer(212) on the first stress layer, in which the second power level is higher than the first power level.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_KR20080060142A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD OF FABRICATING SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T18%3A37%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PARK,%20JAE%20EON&rft.date=2008-07-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20080060142A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true