NAND TYPE FLASH MEMORY DEVICE WITH PAGE BUFFER AND METHOD FOR READING DATA OF THE SAME

A NAND flash memory device with a page buffer and a method for reading data of the same are provided to verify state of a memory cell stably during read operation to verify program and erase state of the memory cell. A memory cell array includes a plurality of cell strings comprising a number of mem...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: KIM, BYONG KOOK
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KIM, BYONG KOOK
description A NAND flash memory device with a page buffer and a method for reading data of the same are provided to verify state of a memory cell stably during read operation to verify program and erase state of the memory cell. A memory cell array includes a plurality of cell strings comprising a number of memory cells, a first selection transistor connected to a bit line and a second selection transistor connected to a common source line. A power supply voltage or a read voltage is supplied to the common source line during data sensing period of the memory cell. A bit line selection part(122) selects one of the bit lines constituting the plurality of cell strings, and precharges the selected bit line with a ground voltage during precharge period. A data latch part(124) is connected to a node, and latches output data outputted from the selected memory cell of the cell string through the bit line selection part during the sensing period, and then outputs the output data according to a latch signal and a potential of an output stage of the bit line selection part. A data input/output part(126) outputs the output data supplied from the data latch part to a data line, or supplies input data inputted from the data line to the data latch part.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20080039107A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20080039107A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20080039107A3</originalsourceid><addsrcrecordid>eNqNyrEKwjAUBdAuDqL-wwVnIdpBOz6blyZokpLGSqdSJE6ihfr_iOAHOJ3lzLPWkZOIXc1QZ2o0LFsfOkhuTcm4mqhRU8U4XpTigO-2HLWXUD4gMEnjKkiKBK8QNaMhy8tsdh8eU1r9XGRrxbHUmzS--jSNwy0907s_hZ0QByHyYiv2lP-3Ptf3MI0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>NAND TYPE FLASH MEMORY DEVICE WITH PAGE BUFFER AND METHOD FOR READING DATA OF THE SAME</title><source>esp@cenet</source><creator>KIM, BYONG KOOK</creator><creatorcontrib>KIM, BYONG KOOK</creatorcontrib><description>A NAND flash memory device with a page buffer and a method for reading data of the same are provided to verify state of a memory cell stably during read operation to verify program and erase state of the memory cell. A memory cell array includes a plurality of cell strings comprising a number of memory cells, a first selection transistor connected to a bit line and a second selection transistor connected to a common source line. A power supply voltage or a read voltage is supplied to the common source line during data sensing period of the memory cell. A bit line selection part(122) selects one of the bit lines constituting the plurality of cell strings, and precharges the selected bit line with a ground voltage during precharge period. A data latch part(124) is connected to a node, and latches output data outputted from the selected memory cell of the cell string through the bit line selection part during the sensing period, and then outputs the output data according to a latch signal and a potential of an output stage of the bit line selection part. A data input/output part(126) outputs the output data supplied from the data latch part to a data line, or supplies input data inputted from the data line to the data latch part.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080507&amp;DB=EPODOC&amp;CC=KR&amp;NR=20080039107A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080507&amp;DB=EPODOC&amp;CC=KR&amp;NR=20080039107A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, BYONG KOOK</creatorcontrib><title>NAND TYPE FLASH MEMORY DEVICE WITH PAGE BUFFER AND METHOD FOR READING DATA OF THE SAME</title><description>A NAND flash memory device with a page buffer and a method for reading data of the same are provided to verify state of a memory cell stably during read operation to verify program and erase state of the memory cell. A memory cell array includes a plurality of cell strings comprising a number of memory cells, a first selection transistor connected to a bit line and a second selection transistor connected to a common source line. A power supply voltage or a read voltage is supplied to the common source line during data sensing period of the memory cell. A bit line selection part(122) selects one of the bit lines constituting the plurality of cell strings, and precharges the selected bit line with a ground voltage during precharge period. A data latch part(124) is connected to a node, and latches output data outputted from the selected memory cell of the cell string through the bit line selection part during the sensing period, and then outputs the output data according to a latch signal and a potential of an output stage of the bit line selection part. A data input/output part(126) outputs the output data supplied from the data latch part to a data line, or supplies input data inputted from the data line to the data latch part.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAUBdAuDqL-wwVnIdpBOz6blyZokpLGSqdSJE6ihfr_iOAHOJ3lzLPWkZOIXc1QZ2o0LFsfOkhuTcm4mqhRU8U4XpTigO-2HLWXUD4gMEnjKkiKBK8QNaMhy8tsdh8eU1r9XGRrxbHUmzS--jSNwy0907s_hZ0QByHyYiv2lP-3Ptf3MI0</recordid><startdate>20080507</startdate><enddate>20080507</enddate><creator>KIM, BYONG KOOK</creator><scope>EVB</scope></search><sort><creationdate>20080507</creationdate><title>NAND TYPE FLASH MEMORY DEVICE WITH PAGE BUFFER AND METHOD FOR READING DATA OF THE SAME</title><author>KIM, BYONG KOOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20080039107A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, BYONG KOOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, BYONG KOOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NAND TYPE FLASH MEMORY DEVICE WITH PAGE BUFFER AND METHOD FOR READING DATA OF THE SAME</title><date>2008-05-07</date><risdate>2008</risdate><abstract>A NAND flash memory device with a page buffer and a method for reading data of the same are provided to verify state of a memory cell stably during read operation to verify program and erase state of the memory cell. A memory cell array includes a plurality of cell strings comprising a number of memory cells, a first selection transistor connected to a bit line and a second selection transistor connected to a common source line. A power supply voltage or a read voltage is supplied to the common source line during data sensing period of the memory cell. A bit line selection part(122) selects one of the bit lines constituting the plurality of cell strings, and precharges the selected bit line with a ground voltage during precharge period. A data latch part(124) is connected to a node, and latches output data outputted from the selected memory cell of the cell string through the bit line selection part during the sensing period, and then outputs the output data according to a latch signal and a potential of an output stage of the bit line selection part. A data input/output part(126) outputs the output data supplied from the data latch part to a data line, or supplies input data inputted from the data line to the data latch part.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_KR20080039107A
source esp@cenet
subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title NAND TYPE FLASH MEMORY DEVICE WITH PAGE BUFFER AND METHOD FOR READING DATA OF THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T04%3A20%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KIM,%20BYONG%20KOOK&rft.date=2008-05-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20080039107A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true