METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device is provided to maintain a step between an alignment key pattern and an interlayer dielectric in a post process by protecting the alignment key pattern by using a protective layer. A substrate(100) including a chip area and a scribe line is prepared....
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| creator | PARK, KYU SUL HONG, WEON CHEOL SHIN, SHANG KYU KIM, HYUN CHANG MA, JONG WAN |
| description | A method for manufacturing a semiconductor device is provided to maintain a step between an alignment key pattern and an interlayer dielectric in a post process by protecting the alignment key pattern by using a protective layer. A substrate(100) including a chip area and a scribe line is prepared. A plurality of alignment key patterns(108) are formed on the scribe line of the substrate. An interlayer dielectric(110) is formed to fill a gap between the alignment key patterns. A protective layer is formed on the alignment key patterns and the interlayer dielectric. A circuit pattern(114) is formed on the chip area of the substrate. A lower pattern and a lower interlayer dielectric are formed on the chip area. The alignment key patterns are formed on the scribe line of the substrate while the lower pattern and the lower interlayer dielectric are formed on the chip area. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20070109018A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20070109018A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20070109018A3</originalsourceid><addsrcrecordid>eNrjZNDzdQ3x8HdR8HdT8HX0C3VzdA4JDfL0c1dwVAh29fV09vdzCXUO8Q9ScHEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgYG5gaGBpYGhhaOxsSpAgBwtSaD</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>PARK, KYU SUL ; HONG, WEON CHEOL ; SHIN, SHANG KYU ; KIM, HYUN CHANG ; MA, JONG WAN</creator><creatorcontrib>PARK, KYU SUL ; HONG, WEON CHEOL ; SHIN, SHANG KYU ; KIM, HYUN CHANG ; MA, JONG WAN</creatorcontrib><description>A method for manufacturing a semiconductor device is provided to maintain a step between an alignment key pattern and an interlayer dielectric in a post process by protecting the alignment key pattern by using a protective layer. A substrate(100) including a chip area and a scribe line is prepared. A plurality of alignment key patterns(108) are formed on the scribe line of the substrate. An interlayer dielectric(110) is formed to fill a gap between the alignment key patterns. A protective layer is formed on the alignment key patterns and the interlayer dielectric. A circuit pattern(114) is formed on the chip area of the substrate. A lower pattern and a lower interlayer dielectric are formed on the chip area. The alignment key patterns are formed on the scribe line of the substrate while the lower pattern and the lower interlayer dielectric are formed on the chip area.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071115&DB=EPODOC&CC=KR&NR=20070109018A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071115&DB=EPODOC&CC=KR&NR=20070109018A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARK, KYU SUL</creatorcontrib><creatorcontrib>HONG, WEON CHEOL</creatorcontrib><creatorcontrib>SHIN, SHANG KYU</creatorcontrib><creatorcontrib>KIM, HYUN CHANG</creatorcontrib><creatorcontrib>MA, JONG WAN</creatorcontrib><title>METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE</title><description>A method for manufacturing a semiconductor device is provided to maintain a step between an alignment key pattern and an interlayer dielectric in a post process by protecting the alignment key pattern by using a protective layer. A substrate(100) including a chip area and a scribe line is prepared. A plurality of alignment key patterns(108) are formed on the scribe line of the substrate. An interlayer dielectric(110) is formed to fill a gap between the alignment key patterns. A protective layer is formed on the alignment key patterns and the interlayer dielectric. A circuit pattern(114) is formed on the chip area of the substrate. A lower pattern and a lower interlayer dielectric are formed on the chip area. The alignment key patterns are formed on the scribe line of the substrate while the lower pattern and the lower interlayer dielectric are formed on the chip area.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDzdQ3x8HdR8HdT8HX0C3VzdA4JDfL0c1dwVAh29fV09vdzCXUO8Q9ScHEN83R25WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8d5BRgYG5gaGBpYGhhaOxsSpAgBwtSaD</recordid><startdate>20071115</startdate><enddate>20071115</enddate><creator>PARK, KYU SUL</creator><creator>HONG, WEON CHEOL</creator><creator>SHIN, SHANG KYU</creator><creator>KIM, HYUN CHANG</creator><creator>MA, JONG WAN</creator><scope>EVB</scope></search><sort><creationdate>20071115</creationdate><title>METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE</title><author>PARK, KYU SUL ; HONG, WEON CHEOL ; SHIN, SHANG KYU ; KIM, HYUN CHANG ; MA, JONG WAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20070109018A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PARK, KYU SUL</creatorcontrib><creatorcontrib>HONG, WEON CHEOL</creatorcontrib><creatorcontrib>SHIN, SHANG KYU</creatorcontrib><creatorcontrib>KIM, HYUN CHANG</creatorcontrib><creatorcontrib>MA, JONG WAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARK, KYU SUL</au><au>HONG, WEON CHEOL</au><au>SHIN, SHANG KYU</au><au>KIM, HYUN CHANG</au><au>MA, JONG WAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE</title><date>2007-11-15</date><risdate>2007</risdate><abstract>A method for manufacturing a semiconductor device is provided to maintain a step between an alignment key pattern and an interlayer dielectric in a post process by protecting the alignment key pattern by using a protective layer. A substrate(100) including a chip area and a scribe line is prepared. A plurality of alignment key patterns(108) are formed on the scribe line of the substrate. An interlayer dielectric(110) is formed to fill a gap between the alignment key patterns. A protective layer is formed on the alignment key patterns and the interlayer dielectric. A circuit pattern(114) is formed on the chip area of the substrate. A lower pattern and a lower interlayer dielectric are formed on the chip area. The alignment key patterns are formed on the scribe line of the substrate while the lower pattern and the lower interlayer dielectric are formed on the chip area.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE |
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