PACKAGE OF WAFER LEVEL SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME
A method for manufacturing a semiconductor chip package of a wafer level is provided to prevent damage of a conductive pattern in a post process by forming external connection terminals on a rear surface of a wafer and covering a front surface with an encapsulation layer. A conductive pattern(102) i...
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| creator | KIM, HEUI SEOG HAN, MAN HEE KIM, SANG JUN SIN, WHA SU KIM, JAE HONG KIM, GOON WOO |
| description | A method for manufacturing a semiconductor chip package of a wafer level is provided to prevent damage of a conductive pattern in a post process by forming external connection terminals on a rear surface of a wafer and covering a front surface with an encapsulation layer. A conductive pattern(102) is formed a front surface of a wafer(100), and the front surface of the wafer is covered by an encapsulation layer(106). Chip plugs(104) are electrically connected to the conductive pattern, and are embedded in a rear surface of the wafer. External connection terminals are formed on the rear surface of the wafer, and are electrically connected to the chip plugs. The uppermost conductive pattern is directly connected to the chip plugs. The encapsulation layer is made of epoxy molding compound. |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | PACKAGE OF WAFER LEVEL SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME |
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