METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging lay...

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Hauptverfasser: ZILBER GIL, OGANESIAN VAGE, AKSENTON JULIA
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator ZILBER GIL
OGANESIAN VAGE
AKSENTON JULIA
description An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20060026953A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20060026953A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20060026953A3</originalsourceid><addsrcrecordid>eNrjZLD1dQ3x8HdRcPQD4oAAxyDHkNBgBTf_IIUAR2dvR3dPP3cFT78QV3eghKuLgrNnkHOoZ4iCi2uYp7NrMA8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstifcOMjIwMDMwMDKzNDV2NCZOFQDBBCqQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES</title><source>esp@cenet</source><creator>ZILBER GIL ; OGANESIAN VAGE ; AKSENTON JULIA</creator><creatorcontrib>ZILBER GIL ; OGANESIAN VAGE ; AKSENTON JULIA</creatorcontrib><description>An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060324&amp;DB=EPODOC&amp;CC=KR&amp;NR=20060026953A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060324&amp;DB=EPODOC&amp;CC=KR&amp;NR=20060026953A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZILBER GIL</creatorcontrib><creatorcontrib>OGANESIAN VAGE</creatorcontrib><creatorcontrib>AKSENTON JULIA</creatorcontrib><title>METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES</title><description>An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD1dQ3x8HdRcPQD4oAAxyDHkNBgBTf_IIUAR2dvR3dPP3cFT78QV3eghKuLgrNnkHOoZ4iCi2uYp7NrMA8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstifcOMjIwMDMwMDKzNDV2NCZOFQDBBCqQ</recordid><startdate>20060324</startdate><enddate>20060324</enddate><creator>ZILBER GIL</creator><creator>OGANESIAN VAGE</creator><creator>AKSENTON JULIA</creator><scope>EVB</scope></search><sort><creationdate>20060324</creationdate><title>METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES</title><author>ZILBER GIL ; OGANESIAN VAGE ; AKSENTON JULIA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20060026953A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ZILBER GIL</creatorcontrib><creatorcontrib>OGANESIAN VAGE</creatorcontrib><creatorcontrib>AKSENTON JULIA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZILBER GIL</au><au>OGANESIAN VAGE</au><au>AKSENTON JULIA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES</title><date>2006-03-24</date><risdate>2006</risdate><abstract>An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T02%3A48%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ZILBER%20GIL&rft.date=2006-03-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20060026953A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true