MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED

MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED

PURPOSE: A multiprogram-mounted architecture based on a DSP(Digital Signal Processor) core is provided to manufacture a chip having various functions by embedding multiple programs in one chip and simply changing the external mode setup, and to prevent the degradation of the performance due to the i...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: KIM, DEUK GYEONG
Format: Patent
Sprache:eng ; kor
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KIM, DEUK GYEONG
description PURPOSE: A multiprogram-mounted architecture based on a DSP(Digital Signal Processor) core is provided to manufacture a chip having various functions by embedding multiple programs in one chip and simply changing the external mode setup, and to prevent the degradation of the performance due to the increase of cycles. CONSTITUTION: The architecture comprises a DSP core(100) generating a program address and receiving various program data signals, a program ROM(200) divided into 2¬z parts, and a chip selection control unit(300) controlling the chip selecting signal of the program ROM. If the program address generated from the DSP core consists of K-bit, the program address is connected to the input address of the program ROM. Then, the addressing of each program ROM is performed. A mode and the program address are inputted to the chip selection control unit. The chip selecting signals of each program ROM are controlled. Thus, various program addressing modes are provided.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_KR20020067751A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>KR20020067751A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_KR20020067751A3</originalsourceid><addsrcrecordid>eNrjZLD0DfUJ8QzwcVUICPL3cnUOUXD1dXJ1cXF1UXAMcvbwDAEKhQa5Krj5Bym4BAcoOPsDOU6Owa4uPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7Uk3jvIyMAAiMzMzU0NHY2JUwUAGyYpXg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED</title><source>esp@cenet</source><creator>KIM, DEUK GYEONG</creator><creatorcontrib>KIM, DEUK GYEONG</creatorcontrib><description>PURPOSE: A multiprogram-mounted architecture based on a DSP(Digital Signal Processor) core is provided to manufacture a chip having various functions by embedding multiple programs in one chip and simply changing the external mode setup, and to prevent the degradation of the performance due to the increase of cycles. CONSTITUTION: The architecture comprises a DSP core(100) generating a program address and receiving various program data signals, a program ROM(200) divided into 2¬z parts, and a chip selection control unit(300) controlling the chip selecting signal of the program ROM. If the program address generated from the DSP core consists of K-bit, the program address is connected to the input address of the program ROM. Then, the addressing of each program ROM is performed. A mode and the program address are inputted to the chip selection control unit. The chip selecting signals of each program ROM are controlled. Thus, various program addressing modes are provided.</description><edition>7</edition><language>eng ; kor</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020824&amp;DB=EPODOC&amp;CC=KR&amp;NR=20020067751A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020824&amp;DB=EPODOC&amp;CC=KR&amp;NR=20020067751A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, DEUK GYEONG</creatorcontrib><title>MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED</title><description>PURPOSE: A multiprogram-mounted architecture based on a DSP(Digital Signal Processor) core is provided to manufacture a chip having various functions by embedding multiple programs in one chip and simply changing the external mode setup, and to prevent the degradation of the performance due to the increase of cycles. CONSTITUTION: The architecture comprises a DSP core(100) generating a program address and receiving various program data signals, a program ROM(200) divided into 2¬z parts, and a chip selection control unit(300) controlling the chip selecting signal of the program ROM. If the program address generated from the DSP core consists of K-bit, the program address is connected to the input address of the program ROM. Then, the addressing of each program ROM is performed. A mode and the program address are inputted to the chip selection control unit. The chip selecting signals of each program ROM are controlled. Thus, various program addressing modes are provided.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD0DfUJ8QzwcVUICPL3cnUOUXD1dXJ1cXF1UXAMcvbwDAEKhQa5Krj5Bym4BAcoOPsDOU6Owa4uPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7Uk3jvIyMAAiMzMzU0NHY2JUwUAGyYpXg</recordid><startdate>20020824</startdate><enddate>20020824</enddate><creator>KIM, DEUK GYEONG</creator><scope>EVB</scope></search><sort><creationdate>20020824</creationdate><title>MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED</title><author>KIM, DEUK GYEONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR20020067751A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2002</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, DEUK GYEONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, DEUK GYEONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED</title><date>2002-08-24</date><risdate>2002</risdate><abstract>PURPOSE: A multiprogram-mounted architecture based on a DSP(Digital Signal Processor) core is provided to manufacture a chip having various functions by embedding multiple programs in one chip and simply changing the external mode setup, and to prevent the degradation of the performance due to the increase of cycles. CONSTITUTION: The architecture comprises a DSP core(100) generating a program address and receiving various program data signals, a program ROM(200) divided into 2¬z parts, and a chip selection control unit(300) controlling the chip selecting signal of the program ROM. If the program address generated from the DSP core consists of K-bit, the program address is connected to the input address of the program ROM. Then, the addressing of each program ROM is performed. A mode and the program address are inputted to the chip selection control unit. The chip selecting signals of each program ROM are controlled. Thus, various program addressing modes are provided.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; kor
recordid cdi_epo_espacenet_KR20020067751A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title MULTIPLE PROJECT EMBEDDED ARCHITECTURE FOR DSP CORE BASED
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T19%3A26%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KIM,%20DEUK%20GYEONG&rft.date=2002-08-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EKR20020067751A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true