METHOD FOR FORMING POLY PLUG OF THIN FILM TRANSISTOR
PURPOSE: A method for forming a poly plug of a thin film transistor is provided to enhance reliability of the thin film transistor by reducing a step difference without a loss of a poly plug. CONSTITUTION: An interlayer dielectric(32) is deposited on a substrate(31). A contact hole is formed by etch...
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| creator | LEE, JEONG UNG CHOI, YUN JE |
| description | PURPOSE: A method for forming a poly plug of a thin film transistor is provided to enhance reliability of the thin film transistor by reducing a step difference without a loss of a poly plug. CONSTITUTION: An interlayer dielectric(32) is deposited on a substrate(31). A contact hole is formed by etching the interlayer dielectric(32). A polysilicon layer is deposited on the interlayer dielectric(32) including the contact hole. The thickness of the polysilicon layer is reduced by etching the polysilicon layer. A photoresist layer is deposited on the polysilicon layer. The photoresist layer is patterned by performing an exposing process and a developing process. A poly plug(33a) is formed by etching the polysilicon layer. A poly gate(35) and a gate oxide layer(36) are formed by depositing and etching a polysilicon layer and an oxide layer. A poly channel layer(37) is formed by depositing a silicon layer on the gate oxide layer(36). A part of the poly gate(35) is exposed by patterning the poly channel layer(37). |
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CONSTITUTION: An interlayer dielectric(32) is deposited on a substrate(31). A contact hole is formed by etching the interlayer dielectric(32). A polysilicon layer is deposited on the interlayer dielectric(32) including the contact hole. The thickness of the polysilicon layer is reduced by etching the polysilicon layer. A photoresist layer is deposited on the polysilicon layer. The photoresist layer is patterned by performing an exposing process and a developing process. A poly plug(33a) is formed by etching the polysilicon layer. A poly gate(35) and a gate oxide layer(36) are formed by depositing and etching a polysilicon layer and an oxide layer. A poly channel layer(37) is formed by depositing a silicon layer on the gate oxide layer(36). A part of the poly gate(35) is exposed by patterning the poly channel layer(37).</description><edition>7</edition><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020712&DB=EPODOC&CC=KR&NR=20020058431A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020712&DB=EPODOC&CC=KR&NR=20020058431A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE, JEONG UNG</creatorcontrib><creatorcontrib>CHOI, YUN JE</creatorcontrib><title>METHOD FOR FORMING POLY PLUG OF THIN FILM TRANSISTOR</title><description>PURPOSE: A method for forming a poly plug of a thin film transistor is provided to enhance reliability of the thin film transistor by reducing a step difference without a loss of a poly plug. CONSTITUTION: An interlayer dielectric(32) is deposited on a substrate(31). A contact hole is formed by etching the interlayer dielectric(32). A polysilicon layer is deposited on the interlayer dielectric(32) including the contact hole. The thickness of the polysilicon layer is reduced by etching the polysilicon layer. A photoresist layer is deposited on the polysilicon layer. The photoresist layer is patterned by performing an exposing process and a developing process. A poly plug(33a) is formed by etching the polysilicon layer. A poly gate(35) and a gate oxide layer(36) are formed by depositing and etching a polysilicon layer and an oxide layer. A poly channel layer(37) is formed by depositing a silicon layer on the gate oxide layer(36). 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CONSTITUTION: An interlayer dielectric(32) is deposited on a substrate(31). A contact hole is formed by etching the interlayer dielectric(32). A polysilicon layer is deposited on the interlayer dielectric(32) including the contact hole. The thickness of the polysilicon layer is reduced by etching the polysilicon layer. A photoresist layer is deposited on the polysilicon layer. The photoresist layer is patterned by performing an exposing process and a developing process. A poly plug(33a) is formed by etching the polysilicon layer. A poly gate(35) and a gate oxide layer(36) are formed by depositing and etching a polysilicon layer and an oxide layer. A poly channel layer(37) is formed by depositing a silicon layer on the gate oxide layer(36). A part of the poly gate(35) is exposed by patterning the poly channel layer(37).</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| title | METHOD FOR FORMING POLY PLUG OF THIN FILM TRANSISTOR |
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