METHOD FOR MAKING A CAPACITOR USING A MULTI-LAYER STRUCTURE

PURPOSE: A method for forming a capacitor using a multi-layer structure is provided to reduce a fabricating cost and improve productivity by increasing the number of chip per wafer in a wafer formation process. CONSTITUTION: The first plug is formed(S10) without reducing an existing pattern size. Th...

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Bibliographische Detailangaben
Hauptverfasser: EOM, TAE SEUNG, KOO, SANG SUL
Format: Patent
Sprache:eng ; kor
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Zusammenfassung:PURPOSE: A method for forming a capacitor using a multi-layer structure is provided to reduce a fabricating cost and improve productivity by increasing the number of chip per wafer in a wafer formation process. CONSTITUTION: The first plug is formed(S10) without reducing an existing pattern size. The first capacitor is formed(S20). The second plug is formed(S30) between patterns of the first capacitor. The second plug is connected with an active region. The second capacitor is formed(S40). In the process for forming the second capacitor, a mask for forming the second capacitor is different from the mask for forming the first capacitor. A double exposure process using the masks twice is performed to form the first and the second capacitors. Accordingly, the capacity of the capacitor is increased by forming the multi-layered capacitor pattern. 본 발명은 다층 구조를 이용한 캐패시터의 제조 방법에 관한 것으로, 1차 플러그를 형성하는 단계; 1차 캐패시터를 형성하는 단계; 2차 플러그를 형성하는 단계; 2차 캐패시터를 형성하는 단계를 포함하며, 소자의 고안 규칙이 축소가 되더라도 기존 패턴의 크기를 줄이지 않고, 공정을 진행할 수 있어 공정의 여유도를 향상할 수 있으며, 더 큰 용량의 확보 및 패턴의 집적도를 향상할 수 있어 소자의 집적도를 향상할 수 있는 효과가 있다.