DELTA-SIGMA MODULATOR WITH REDUCED POWER CONSUMPTION AND PACEMAKER USING THIS

A delta-sigma modulator with reduced power consumption and a placemaker using the same is provided to secure correction action by minimizing the consumed power of a delta-sigma modulator and minimizing the nonlinear characteristics. A delta-sigma modulator with reduced power consumption and a placemaker using the same includes a digital block, a current source(331), a first current mirror(332), a bias adjusting transistor(333), a second current mirror(334) and a switched capacity circuit. The digital block produces any one of clock signal among clock signals of different duty ratios and applies the produced clock signal to the bias adjusting transistor and the switched capacitor circuit. The switched capacity circuit performs any one operation among a sample mode and an integration mode on the clock signal applied from the digital block by applying the current of a second output as bias current.