NONVOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME
Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunnelin...
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creator | JEONG, YOUNG CHEON HA, SOUNG YOUB MOON, JUNG HO PARK, JAE HYUN KWON, CHUL SOON LIM, BYEONG CHEOL YU, JAE MIN |
description | Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer. |
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The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.</description><language>eng</language><subject>ELECTRICITY</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070412&DB=EPODOC&CC=KR&NR=100706804B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070412&DB=EPODOC&CC=KR&NR=100706804B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JEONG, YOUNG CHEON</creatorcontrib><creatorcontrib>HA, SOUNG YOUB</creatorcontrib><creatorcontrib>MOON, JUNG HO</creatorcontrib><creatorcontrib>PARK, JAE HYUN</creatorcontrib><creatorcontrib>KWON, CHUL SOON</creatorcontrib><creatorcontrib>LIM, BYEONG CHEOL</creatorcontrib><creatorcontrib>YU, JAE MIN</creatorcontrib><title>NONVOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME</title><description>Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD08_cL8_dxDPH0cVXwdfX1D4pUcHEN83R2VXD0cwGKhHj4uyi4-QeBsK-nn7tCiIerQrCjrysPA2taYk5xKi-U5mZQdnMNcfbQTS3Ij08tLkhMTs1LLYn3DjI0MDA3MLMwMHFyMjQmThUAH9cpgA</recordid><startdate>20070412</startdate><enddate>20070412</enddate><creator>JEONG, YOUNG CHEON</creator><creator>HA, SOUNG YOUB</creator><creator>MOON, JUNG HO</creator><creator>PARK, JAE HYUN</creator><creator>KWON, CHUL SOON</creator><creator>LIM, BYEONG CHEOL</creator><creator>YU, JAE MIN</creator><scope>EVB</scope></search><sort><creationdate>20070412</creationdate><title>NONVOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME</title><author>JEONG, YOUNG CHEON ; HA, SOUNG YOUB ; MOON, JUNG HO ; PARK, JAE HYUN ; KWON, CHUL SOON ; LIM, BYEONG CHEOL ; YU, JAE MIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR100706804BB13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>JEONG, YOUNG CHEON</creatorcontrib><creatorcontrib>HA, SOUNG YOUB</creatorcontrib><creatorcontrib>MOON, JUNG HO</creatorcontrib><creatorcontrib>PARK, JAE HYUN</creatorcontrib><creatorcontrib>KWON, CHUL SOON</creatorcontrib><creatorcontrib>LIM, BYEONG CHEOL</creatorcontrib><creatorcontrib>YU, JAE MIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEONG, YOUNG CHEON</au><au>HA, SOUNG YOUB</au><au>MOON, JUNG HO</au><au>PARK, JAE HYUN</au><au>KWON, CHUL SOON</au><au>LIM, BYEONG CHEOL</au><au>YU, JAE MIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NONVOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME</title><date>2007-04-12</date><risdate>2007</risdate><abstract>Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.</abstract><oa>free_for_read</oa></addata></record> |
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title | NONVOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME |
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