MEMORY CONTROLLER WITHIN A DATA PROCESSING SYSTEM FOR CACHING STACK OPERATIONS AND PREFETCHING DATA FROM MEMORY

An improved memory controller (20) within a data processing system (10) having a look-aside cache architecture is disclosed. The data processing system (10) includes a processor (12) having an upper level cache (14) associated therewith, a memory controller (20) having an associated controller memory (48), a processor bus (18) coupled between the processor and the memory controller (20), and a main memory (22). The data processing system (10) further includes a lower level cache (16) coupled to the processor bus (18) in parallel with the processor (12) and memory controller (20). According to a first aspect of the present invention, the memory controller (20) includes logic, which in response to receipt of a write request that will not be serviced by the lower level cache (16) and for which the associated data is not a replaced modified cache line, stores the associated data within the controller memory (48) associated with the memory controller (20), thereby optimizing data storage within the data processing system (10). According to a second aspect of the present invention, the memory controller (20) includes logic, which in response to receipt of a request for information residing only in main memory (22), fetches the requested information from main memory (22) and stores additional information adjacent to said requested data in main memory (22) within a prefetch buffer (44, 46), thereby minimizing access time to the prefetched information.