THIN FILM TRANSISTOR AND MAKING METHOD
도전형이 다른 폴리실리콘층이 접속되는 구성을 한 박막트랜지스터에서 불순물이 확산 함으로서 좋지 않은 상태의 발생을 방지한 박막 트랜지스터 및 그 제조방법을 제공한다. 드레인 6, 채널7, 소스8은 제 2산화막4의 표면상에, 폴리실리콘으로서 일체로 형성 되여 있다. 드레인 6은 패드층3 (제 2의 다결정 반도체층)의 상면에 이르도록 형성된 콘택트 홀5를 통해서,패드층3에 접속하도록 형성되어 있다. 그리고 콘택트 홀5 (개구부)의 저부에 위치하는 패드층3에 붕소 주입 영역BR가 형성 되여 있다. Provided are a thin-fi...
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| creator | KIM, IL-JUNG MAEGAWA, SHIGETO TSUTSUMI, KAZUHITO IPPOSHI, TAKASHI KURIYAMA, HIROTADA UKITA, MOTORU MAEDA, SHIGUNOBU IWAMATSU, TOSHIAKI TSUTSUMI, TOSHIAKI ISHIGAKI, YOSHIYUKI |
| description | 도전형이 다른 폴리실리콘층이 접속되는 구성을 한 박막트랜지스터에서 불순물이 확산 함으로서 좋지 않은 상태의 발생을 방지한 박막 트랜지스터 및 그 제조방법을 제공한다. 드레인 6, 채널7, 소스8은 제 2산화막4의 표면상에, 폴리실리콘으로서 일체로 형성 되여 있다. 드레인 6은 패드층3 (제 2의 다결정 반도체층)의 상면에 이르도록 형성된 콘택트 홀5를 통해서,패드층3에 접속하도록 형성되어 있다. 그리고 콘택트 홀5 (개구부)의 저부에 위치하는 패드층3에 붕소 주입 영역BR가 형성 되여 있다.
Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain ( 6 ), a channel ( 7 ) and a source ( 8 ) are integrally formed on a surface of a second oxide film ( 4 ) by polysilicon. The drain ( 6 ) is formed to be connected with a pad layer ( 3 ) (second polycrystalline semiconductor layer) through a contact hole ( 5 ) which is formed to reach an upper surface of the pad layer ( 3 ). The pad layer ( 3 ) positioned on a bottom portion of the contact hole ( 5 ) (opening) is provided with a boron implantation region BR. |
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Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain ( 6 ), a channel ( 7 ) and a source ( 8 ) are integrally formed on a surface of a second oxide film ( 4 ) by polysilicon. The drain ( 6 ) is formed to be connected with a pad layer ( 3 ) (second polycrystalline semiconductor layer) through a contact hole ( 5 ) which is formed to reach an upper surface of the pad layer ( 3 ). The pad layer ( 3 ) positioned on a bottom portion of the contact hole ( 5 ) (opening) is provided with a boron implantation region BR.</description><edition>7</edition><language>eng ; kor</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000601&DB=EPODOC&CC=KR&NR=100258378B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000601&DB=EPODOC&CC=KR&NR=100258378B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, IL-JUNG</creatorcontrib><creatorcontrib>MAEGAWA, SHIGETO</creatorcontrib><creatorcontrib>TSUTSUMI, KAZUHITO</creatorcontrib><creatorcontrib>IPPOSHI, TAKASHI</creatorcontrib><creatorcontrib>KURIYAMA, HIROTADA</creatorcontrib><creatorcontrib>UKITA, MOTORU</creatorcontrib><creatorcontrib>MAEDA, SHIGUNOBU</creatorcontrib><creatorcontrib>IWAMATSU, TOSHIAKI</creatorcontrib><creatorcontrib>TSUTSUMI, TOSHIAKI</creatorcontrib><creatorcontrib>ISHIGAKI, YOSHIYUKI</creatorcontrib><title>THIN FILM TRANSISTOR AND MAKING METHOD</title><description>도전형이 다른 폴리실리콘층이 접속되는 구성을 한 박막트랜지스터에서 불순물이 확산 함으로서 좋지 않은 상태의 발생을 방지한 박막 트랜지스터 및 그 제조방법을 제공한다. 드레인 6, 채널7, 소스8은 제 2산화막4의 표면상에, 폴리실리콘으로서 일체로 형성 되여 있다. 드레인 6은 패드층3 (제 2의 다결정 반도체층)의 상면에 이르도록 형성된 콘택트 홀5를 통해서,패드층3에 접속하도록 형성되어 있다. 그리고 콘택트 홀5 (개구부)의 저부에 위치하는 패드층3에 붕소 주입 영역BR가 형성 되여 있다.
Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain ( 6 ), a channel ( 7 ) and a source ( 8 ) are integrally formed on a surface of a second oxide film ( 4 ) by polysilicon. The drain ( 6 ) is formed to be connected with a pad layer ( 3 ) (second polycrystalline semiconductor layer) through a contact hole ( 5 ) which is formed to reach an upper surface of the pad layer ( 3 ). The pad layer ( 3 ) positioned on a bottom portion of the contact hole ( 5 ) (opening) is provided with a boron implantation region BR.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAL8fD0U3Dz9PFVCAly9Av2DA7xD1Jw9HNR8HX09vRzV_B1DfHwd-FhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHeQYYGBkamFsbmFk5OhsbEqQIARsokdA</recordid><startdate>20000601</startdate><enddate>20000601</enddate><creator>KIM, IL-JUNG</creator><creator>MAEGAWA, SHIGETO</creator><creator>TSUTSUMI, KAZUHITO</creator><creator>IPPOSHI, TAKASHI</creator><creator>KURIYAMA, HIROTADA</creator><creator>UKITA, MOTORU</creator><creator>MAEDA, SHIGUNOBU</creator><creator>IWAMATSU, TOSHIAKI</creator><creator>TSUTSUMI, TOSHIAKI</creator><creator>ISHIGAKI, YOSHIYUKI</creator><scope>EVB</scope></search><sort><creationdate>20000601</creationdate><title>THIN FILM TRANSISTOR AND MAKING METHOD</title><author>KIM, IL-JUNG ; MAEGAWA, SHIGETO ; TSUTSUMI, KAZUHITO ; IPPOSHI, TAKASHI ; KURIYAMA, HIROTADA ; UKITA, MOTORU ; MAEDA, SHIGUNOBU ; IWAMATSU, TOSHIAKI ; TSUTSUMI, TOSHIAKI ; ISHIGAKI, YOSHIYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_KR100258378BB13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; kor</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, IL-JUNG</creatorcontrib><creatorcontrib>MAEGAWA, SHIGETO</creatorcontrib><creatorcontrib>TSUTSUMI, KAZUHITO</creatorcontrib><creatorcontrib>IPPOSHI, TAKASHI</creatorcontrib><creatorcontrib>KURIYAMA, HIROTADA</creatorcontrib><creatorcontrib>UKITA, MOTORU</creatorcontrib><creatorcontrib>MAEDA, SHIGUNOBU</creatorcontrib><creatorcontrib>IWAMATSU, TOSHIAKI</creatorcontrib><creatorcontrib>TSUTSUMI, TOSHIAKI</creatorcontrib><creatorcontrib>ISHIGAKI, YOSHIYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, IL-JUNG</au><au>MAEGAWA, SHIGETO</au><au>TSUTSUMI, KAZUHITO</au><au>IPPOSHI, TAKASHI</au><au>KURIYAMA, HIROTADA</au><au>UKITA, MOTORU</au><au>MAEDA, SHIGUNOBU</au><au>IWAMATSU, TOSHIAKI</au><au>TSUTSUMI, TOSHIAKI</au><au>ISHIGAKI, YOSHIYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THIN FILM TRANSISTOR AND MAKING METHOD</title><date>2000-06-01</date><risdate>2000</risdate><abstract>도전형이 다른 폴리실리콘층이 접속되는 구성을 한 박막트랜지스터에서 불순물이 확산 함으로서 좋지 않은 상태의 발생을 방지한 박막 트랜지스터 및 그 제조방법을 제공한다. 드레인 6, 채널7, 소스8은 제 2산화막4의 표면상에, 폴리실리콘으로서 일체로 형성 되여 있다. 드레인 6은 패드층3 (제 2의 다결정 반도체층)의 상면에 이르도록 형성된 콘택트 홀5를 통해서,패드층3에 접속하도록 형성되어 있다. 그리고 콘택트 홀5 (개구부)의 저부에 위치하는 패드층3에 붕소 주입 영역BR가 형성 되여 있다.
Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain ( 6 ), a channel ( 7 ) and a source ( 8 ) are integrally formed on a surface of a second oxide film ( 4 ) by polysilicon. The drain ( 6 ) is formed to be connected with a pad layer ( 3 ) (second polycrystalline semiconductor layer) through a contact hole ( 5 ) which is formed to reach an upper surface of the pad layer ( 3 ). The pad layer ( 3 ) positioned on a bottom portion of the contact hole ( 5 ) (opening) is provided with a boron implantation region BR.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| title | THIN FILM TRANSISTOR AND MAKING METHOD |
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