TEST CIRCUIT AND ITS METHOD OF A SEMICONDUCTOR MEMORY DEVICE

A multi-bit test circuit detects the fail cells in a memory block accurately even though there exists a short bridge between bit lines or between memory cells. The circuit includes an input buffer for transferring a same test data bit received from a multi-bit input/output pin to selected ones of th...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LEE, HEEUN, LEE, JAE-HYUNG
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!