QUASI RANDOM BINARY SEQUENCE GENERATOR

PURPOSE: To enhance a degree of non-prediction performance by providing two re-circulation loops, connecting each of data input terminals of a selection means to each loop and connecting each of address input terminals of the selection means to each loop. CONSTITUTION: A selection circuit M is provided with five address input terminals A0 -A4 and 32 sets of data input terminals B0 -B31 and a circuit 5 is used to select any of the data input terminals to its output side according to an address word fed to the terminals A0 -A4 . In the case of the operation, two shift registers S, T are simultaneously operated by a clock signal. To the terminals A0 -A4 of the circuit M, 31 bits of a pseudo random binary sequence held by the register T are supplied. Any of these bits is selected as an output momentarily and optionally. The selected bit is determined by the contents of the 5 first shift register stages of the register S. Thus, even when the contents of the register T are known, it is difficult to predict number of outputs.