ARITHMETIC UNIT

PURPOSE:To reduce signal delay time and heighten performance by providing plural computing elements, an output data register, converted data register and plural converters as exclusive logical sum circuit. CONSTITUTION:The bit width of input data 151, 152 and output data register 102 are made to 8 b...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	UDA TOSHIYUKI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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