SEMICONDUCTOR STORAGE DEVICE

SEMICONDUCTOR STORAGE DEVICE

PURPOSE:To reduce the number of gates and to quicken readout speed by using a sense amplifier amplifying a readout signal of an ECL (Emitter Coupled Logic) bipolar memory cell so as to drive an output transistor (TR) directly through the amplification of a potential difference between bit line pairs...

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1. Verfasser: KUMADA MASASHI
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator KUMADA MASASHI
description PURPOSE:To reduce the number of gates and to quicken readout speed by using a sense amplifier amplifying a readout signal of an ECL (Emitter Coupled Logic) bipolar memory cell so as to drive an output transistor (TR) directly through the amplification of a potential difference between bit line pairs. CONSTITUTION:A TR Q15 is turned ON, a TR Q16 is turned OFF always at the readout in a sense amplifier circuit 4. The emitter of an output emitter follower TR Q17 is connected to an output terminal Dout, with a potential at a node N6 at 'H' level, the potential of the output terminal Dout goes to 'H' level. With the state of a memory cell C00 at '0' level, a TR Q1 is turned OFF and a TR Q2 is turned ON, the relation of VC>VB, VB02>VB01 in bit line signal voltages and the TR Q31 is turned ON and a node N6 is at 'L' level, and then the potential of the output terminal Dout goes to 'L' level. Then number of conversion gates is reduced to 3 stages from 5 stages to quicken the readout speed.
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CONSTITUTION:A TR Q15 is turned ON, a TR Q16 is turned OFF always at the readout in a sense amplifier circuit 4. The emitter of an output emitter follower TR Q17 is connected to an output terminal Dout, with a potential at a node N6 at 'H' level, the potential of the output terminal Dout goes to 'H' level. With the state of a memory cell C00 at '0' level, a TR Q1 is turned OFF and a TR Q2 is turned ON, the relation of VC&gt;VB, VB02&gt;VB01 in bit line signal voltages and the TR Q31 is turned ON and a node N6 is at 'L' level, and then the potential of the output terminal Dout goes to 'L' level. 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CONSTITUTION:A TR Q15 is turned ON, a TR Q16 is turned OFF always at the readout in a sense amplifier circuit 4. The emitter of an output emitter follower TR Q17 is connected to an output terminal Dout, with a potential at a node N6 at 'H' level, the potential of the output terminal Dout goes to 'H' level. With the state of a memory cell C00 at '0' level, a TR Q1 is turned OFF and a TR Q2 is turned ON, the relation of VC&gt;VB, VB02&gt;VB01 in bit line signal voltages and the TR Q31 is turned ON and a node N6 is at 'L' level, and then the potential of the output terminal Dout goes to 'L' level. Then number of conversion gates is reduced to 3 stages from 5 stages to quicken the readout speed.</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title SEMICONDUCTOR STORAGE DEVICE
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