SERIAL PROCESSING SYSTEM FOR LARGE-CAPACITY DATA

PURPOSE:To simplify a logic circuit and to form a large-capacity and high-speed FIFO by using an up-down counter and a dual port memory to a logic circuit for monitor of memory idle/busy states. CONSTITUTION:When a write permission signal 8 is produced from a control circuit 1, data are supplied to a port 6 from an external device synchronously with an input clock signal 10. Thus data are written into a dual port memory 5 with the contents of a counter 2 of that time pint used as an address. At the same time, the counter 2 and an up-down counter 4 are counted up by the clock signals 12 sent from the circuit 1. While if a read permission signal 9 is produced to outside from the circuit 1, an input clock signal 11 is supplied from thee external device. Then the data are read out of the memory 5 with the contents of a counter 3 used as an address and outputted to a port 7.